Method of forming a semiconductor memory device with a laterally etched bottom dielectric layer
View Patent ↗A semiconductor memory device and a method of forming the same, the semiconductor memory device includes a substrate, a dielectric layer, plural bit lines, at least one bit line contact, a spacer structure and a spacer layer. The substrate has an isolation area to define plural active areas. The dielectric layer is disposed on the substrate, and the dielectric layer includes a bottom layer having a sidewall being retracted from sidewalls of other layers of the dielectric layer. The plural bit lines are disposed on the dielectric stacked structure, along a direction, and the at least one bit line contact is disposed below one of the bit lines, within the substrate. The spacer structure is disposed at sidewalls of each of the bit lines, and the spacer layer is disposed on the spacer structure to directly in contact with the spacer structure and the other layers of the dielectric layer.
1. A method of forming a semiconductor memory device, comprising:
providing a substrate having an isolation area to define a plurality of active areas therein;
forming a dielectric layer on the substrate, only a bottom portion of the dielectric layer being laterally etched, wherein the forming of the dielectric layer comprises:
forming a dielectric material layer on the substrate, to cover the isolation area and the active areas, the dielectric material layer comprising a multilayer structure; and
patterning a portion of the multilayer structure;
forming a plurality of bit lines on the dielectric layer, along a direction;
forming at least one bit line contact below one of the bit lines, in the substrate;
forming a spacer structure on sidewalls of each of the bit lines, wherein the forming of the spacer structure comprises:
forming a first material layer covering the bit lines and the multilayer structure;
forming a second material layer covering the first material layer; and
patterning the second material layer and the first material layer while patterning the portion of the multilayer structure, to form the spacer structure and to leave a bottom layer of the multilayer structure being laterally protruded from the spacer structure; and
forming a spacer layer on sidewalls of the spacer structure, the spacer layer directly in contact with the spacer structure and sidewalls of other portions of the dielectric layer.
2. The method of forming a semiconductor memory device according to claim 1 , wherein the sidewalls of the spacer structure are vertically aligned with the sidewalls of other portions of the multilayer structure after patterning the portion of the multilayer structure.
3. The method of forming a semiconductor memory device according to claim 1 , wherein the forming of the spacer layer comprises:
forming a spacer material layer covering the spacer structure and the multilayer structure; and
patterning the spacer material layer to expose the bottom layer of the multilayer structure.
4. The method of forming a semiconductor memory device according to claim 3 , further comprising:
performing an etching process to only remove the bottom layer of the multilayer structure, to form the dielectric layer.
5. The method of forming a semiconductor memory device according to claim 4 , wherein the etching process is performed after the spacer layer is formed.
6. The method of forming a semiconductor memory device according to claim 1 , wherein the spacer structure comprises a first spacer and a second spacer, and the first spacer is also formed on two sides of the at least one bit line contact.
7. The method of forming a semiconductor memory device according to claim 6 , wherein a sidewall of the bottom portion of the dielectric layer is disposed under the first spacer.
8. The method of forming a semiconductor memory device according to claim 1 , wherein a sidewall of the bottom layer of the dielectric layer is disposed under the bit lines.
9. The method of forming a semiconductor memory device according to claim 1 , wherein the dielectric layer comprises an oxide-nitride-oxide structure.