Non-volatile memory structure
View Patent ↗A non-volatile memory structure including a substrate, a stacked structure, a conductive pillar, a channel layer, a charge storage structure, and a second dielectric layer is provided. The stacked structure is disposed on the substrate and has an opening. The stacked structure includes first conductive layers and first dielectric layers alternately stacked. The conductive pillar is disposed in the opening. The channel layer is disposed between the stacked structure and the conductive pillar. The charge storage structure is disposed between the stacked structure and the channel layer. The second dielectric layer is disposed between the channel layer and the conductive pillar. The non-volatile memory structure can effectively improve the electrical performance and the reliability of the memory device.
1. A non-volatile memory structure, comprising:
a substrate;
a stacked structure disposed on the substrate and having an opening, wherein the stacked structure comprises first conductive layers and first dielectric layers alternately stacked;
a conductive pillar disposed in the opening;
a channel layer disposed between the stacked structure and the conductive pillar;
a charge storage structure disposed between the stacked structure and the channel layer; and
a second dielectric layer disposed between the channel layer and the conductive pillar.
2. The non-volatile memory structure according to claim 1 , wherein a material of the first conductive layers comprises metal or doped polysilicon.
3. The non-volatile memory structure according to claim 1 , wherein a material of the first dielectric layers comprises silicon oxide.
4. The non-volatile memory structure according to claim 1 , wherein a material of the conductive pillar comprises metal or doped polysilicon.
5. The non-volatile memory structure according to claim 1 , wherein the channel layer is further disposed between the conductive pillar and the substrate.
6. The non-volatile memory structure according to claim 1 , wherein a material of the channel layer comprises polysilicon.
7. The non-volatile memory structure according to claim 1 , wherein the charge storage structure comprises:
a charge storage layer disposed between the stacked structure and the channel layer;
a third dielectric layer disposed between the stacked structure and the charge storage layer; and
a fourth dielectric layer disposed between the charge storage layer and the channel layer.
8. The non-volatile memory structure according to claim 7 , wherein the charge storage layer comprises a charge trapping layer.
9. The non-volatile memory structure according to claim 7 , wherein a material of the charge storage layer comprises silicon nitride.
10. The non-volatile memory structure according to claim 7 , wherein a material of the third dielectric layer and the fourth dielectric layer comprises silicon oxide.
11. The non-volatile memory structure according to claim 1 , wherein a material of the second dielectric layer comprises silicon oxide.
12. The non-volatile memory structure according to claim 1 , further comprising:
a semiconductor layer disposed between the channel layer and the substrate.
13. The non-volatile memory structure according to claim 12 , wherein a material of the semiconductor layer comprises epitaxial silicon.
14. The non-volatile memory structure according to claim 1 , further comprising:
a second conductive layer disposed above an uppermost layer of the first conductive layers and connected to the channel layer, wherein the second conductive layer and the uppermost layer of the first conductive layers are isolated from each other.
15. The non-volatile memory structure according to claim 14 , wherein the first dielectric layer is disposed between the second conductive layer and the uppermost layer of the first conductive layers.
16. The non-volatile memory structure according to claim 14 , wherein a material of the second conductive layer comprises doped polysilicon.
17. The non-volatile memory structure according to claim 14 , further comprising:
a contact electrically connected to the second conductive layer.
18. The non-volatile memory structure according to claim 1 , further comprising:
a pad disposed on the conductive pillar, wherein the pad and the channel layer are isolated from each other.
19. The non-volatile memory structure according to claim 18 , wherein the second dielectric layer is further disposed between the pad and the channel layer.
20. The non-volatile memory structure according to claim 18 , further comprising:
a contact electrically connected to the pad.