Three-dimensional semiconductor device
A three-dimensional semiconductor device includes: a peripheral circuit structure disposed on a lower substrate, and including an internal peripheral pad portion; an upper substrate disposed on the peripheral circuit structure; a stack structure disposed on the upper substrate, and including gate horizontal patterns; a vertical channel structure passing through the stack structure in a first region on the upper substrate; a first vertical support structure passing through the stack structure in a second region on the upper substrate; and an internal peripheral contact structure passing through the stack structure and the upper substrate, and electrically connected to the internal peripheral pad portion, wherein an upper surface of the first vertical support structure is disposed on a different level from an upper surface of the vertical channel structure, and is coplanar with an upper surface of the internal peripheral contact structure.
1. A semiconductor device comprising:
a peripheral circuit structure disposed on a lower substrate, and including a peripheral pad portion;
an upper substrate disposed on the peripheral circuit structure;
a stack structure disposed on the upper substrate, and including gate horizontal patterns, the gate horizontal patterns being stacked while being spaced apart from each other in a vertical direction perpendicular to an upper surface of the upper substrate;
a vertical channel structure passing through the stack structure in a first region on the upper substrate;
a vertical support structure passing through the stack structure in a second region on the upper substrate;
a separation structure passing through the stack structure in the first and second regions; and
a peripheral contact plug electrically connected to the peripheral pad portion,
wherein the stack structure has a stepped shape in the second region,
wherein the vertical channel structure includes a lower channel portion, an upper channel portion on the lower channel portion, and an intermediate channel portion between the lower channel portion and the upper channel portion,
wherein the lower channel portion includes a lower channel side surface having a first slope,
wherein the upper channel portion includes an upper channel side surface having a second slope,
wherein at least a portion of the intermediate channel portion includes an intermediate channel side surface having a third slope different from the first and second slopes,
wherein the vertical support structure includes:
a lower support portion disposed at the same level as the lower channel portion;
an intermediate support portion disposed at the same level as the intermediate channel portion; and
an upper support portion disposed at the same level as the upper channel portion, and
wherein a side surface of the lower support portion, a side surface of the intermediate support portion and a side surface of the upper support portion are aligned with each other.
2. The semiconductor device according to claim 1 ,
wherein the peripheral contact plug includes:
a lower plug portion disposed at the same level as the lower channel portion;
an intermediate plug portion disposed at the same level as the intermediate channel portion; and
an upper plug portion disposed at the same level as the upper channel portion, and
wherein a side surface of the lower plug portion, a side surface of the intermediate plug portion and a side surface of the upper plug portion are aligned with each other.
3. The semiconductor device according to claim 2 ,
wherein the intermediate channel side surface extends from the upper channel side surface to lower channel side surface, and
wherein the upper channel side surface is not aligned with the lower channel side surface.
4. The semiconductor device according to claim 3 , wherein the first slope is substantially the same as the second slope.
5. The semiconductor device according to claim 1 ,
wherein the gate horizontal patterns include an uppermost gate horizontal pattern and a lowermost gate horizontal pattern,
wherein the vertical support structure includes an upper portion positioned at the same level as an upper surface of the uppermost gate horizontal pattern and a lower portion positioned at the same level as a lower surface of the lowermost gate horizontal pattern,
wherein a width of the upper portion of the vertical support structure is greater than a width of the lower portion of the vertical support structure, and
wherein a width of the vertical support structure monotonically changes between the upper portion and the lower portion.
6. The semiconductor device according to claim 1 , wherein the stack structure includes a lower stack structure and an upper stack structure on the lower stack structure,
wherein the lower stack structure includes a plurality of lower gate horizontal patterns among the gate horizontal patterns,
wherein the upper stack structure includes a plurality of upper gate horizontal patterns among the gate horizontal patterns,
wherein the lower channel portion faces the plurality of lower gate horizontal patterns, and
wherein the upper channel portion faces the plurality of upper gate horizontal patterns.
7. The semiconductor device according to claim 6 ,
wherein the lower stack structure further includes a plurality of lower insulating layers alternately stacked with the plurality of lower gate horizontal patterns,
wherein the upper stack structure further includes a plurality of upper insulating layers alternately stacked with the plurality of lower gate horizontal patterns,
wherein the stack structure further includes an intermediate insulating layer between a lowermost gate pattern among the plurality of upper gate horizontal patterns and an uppermost gate pattern among the plurality of lower gate horizontal patterns, and
wherein the at least a portion of the intermediate channel portion faces the intermediate insulating layer.
8. The semiconductor device according to claim 7 , wherein a thickness of the intermediate insulating layer is substantially the same as a thickness of any one of the plurality of upper insulating layers or a thickness of any one of the plurality of lower insulating layers.
9. The semiconductor device according to claim 1 , further comprising:
a bit line contact plug on and electrically connected to the vertical channel structure; and
a bit line on and electrically connected to the bit line contact plug,
wherein the gate horizontal patterns includes word lines, and
wherein the vertical channel structure includes:
an insulating core pattern;
a channel layer between the insulating core pattern and the gate horizontal patterns;
a pad pattern on the insulating core pattern and electrically connected to the channel layer; and
a data storage layer between the channel layer and the word lines, and
wherein the vertical support structure is electrically unconnected to the bit line.
10. The semiconductor device according to claim 1 ,
wherein word lines in the second region have a stepped shape having substantially uniform slope in a first direction,
wherein the stepped shape of the word lines is defined by word line pads of the word lines arranged in the first direction, and
wherein the separation structure has a line shape extending in the first direction in a plan view.
11. The semiconductor device according to claim 1 ,
wherein the upper substrate includes a silicon layer,
wherein the vertical channel structure contacts the silicon layer of the upper substrate,
wherein the vertical support structure contacts the silicon layer of the upper substrate,
wherein a lower surface of the contact plug contacts the peripheral pad portion,
wherein the lower surface of the contact plug is at a lower level than the upper substrate, and
wherein an upper surface of the peripheral contact plug is at a higher level than an upper surface of the vertical channel structure.
12. The semiconductor device according to claim 1 , wherein the separation structure includes a conductive core pattern and an insulating spacer on a side surface of the conductive core pattern.
13. A semiconductor device comprising:
a peripheral circuit structure disposed on a lower substrate, and including a peripheral pad portion;
an upper substrate disposed on the peripheral circuit structure;
a stack structure disposed on the upper substrate, and including gate horizontal patterns, the gate horizontal patterns being stacked while being spaced apart from each other in a vertical direction perpendicular to an upper surface of the upper substrate;
a vertical channel structure passing through the stack structure in a first region on the upper substrate;
a vertical support structure passing through the stack structure in a second region on the upper substrate;
a separation structure passing through the stack structure in the first and second regions; and
a peripheral contact plug electrically connected to the peripheral pad portion,
wherein the stack structure has a stepped shape in the second region,
wherein an upper surface of the peripheral contact plug is at a higher level than an upper surface of the vertical channel structure,
wherein the vertical channel structure includes a lower channel portion, an upper channel portion on the lower channel portion, and an intermediate channel portion between the lower channel portion and the upper channel portion,
wherein the lower channel portion includes a lower channel side surface,
wherein the upper channel portion includes an upper channel side surface,
wherein the intermediate channel portion includes an intermediate channel side surface,
wherein the vertical channel structure has an imaginary straight line extending from a center of a lower surface of the lower channel portion to a center of an upper surface of the upper channel portion,
wherein a distance between the imaginary straight line and the lower channel side surface adjacent to the intermediate channel side surface is greater than a distance between the imaginary straight line and the upper channel side surface adjacent to the intermediate channel side surface,
wherein the vertical support structure includes:
a lower support portion disposed at the same level as the lower channel portion;
an intermediate support portion disposed at the same level as the intermediate channel portion; and
an upper support portion disposed at the same level as the upper channel portion, and
wherein a side surface of the lower support portion, a side surface of the intermediate support portion and a side surface of the upper support portion are aligned with each other
wherein the peripheral contact plug includes:
a lower plug portion disposed at the same level as the lower channel portion;
an intermediate plug portion disposed at the same level as the intermediate channel portion; and
an upper plug portion disposed at the same level as the upper channel portion, and
wherein a side surface of the lower plug portion, a side surface of the intermediate plug portion and a side surface of the upper plug portion are aligned with each other.
14. The semiconductor device according to claim 13 , wherein the lower channel portion adjacent to the intermediate channel portion has a first width,
wherein the upper channel portion adjacent to the intermediate channel portion has a second width,
wherein the intermediate channel portion has a third width,
wherein the first width is greater than the second width, and
wherein the third width is greater than each of the first width and the second width.
15. The semiconductor device according to claim 13 , wherein the stack structure includes a lower stack structure and an upper stack structure on the lower stack structure,
wherein the lower stack structure includes a plurality of lower gate horizontal patterns among the gate horizontal patterns,
wherein the upper stack structure includes a plurality of upper gate horizontal patterns among the gate horizontal patterns,
wherein the lower channel portion faces the plurality of lower gate horizontal patterns, and
wherein the upper channel portion faces the plurality of upper gate horizontal patterns.
16. The semiconductor device according to claim 13 , further comprising:
a bit line contact plug on and electrically connected to the vertical channel structure; and
a bit line on and electrically connected to the bit line contact plug,
wherein the gate horizontal patterns includes word lines, and
wherein the vertical channel structure includes:
an insulating core pattern;
a channel layer between the insulating core pattern and the gate horizontal patterns;
a pad pattern on the insulating core pattern and electrically connected to the channel layer; and
a data storage layer between the channel layer and the word lines, and
wherein the vertical support structure is electrically unconnected to the bit line.
17. A semiconductor device comprising:
a peripheral circuit structure disposed on a lower substrate, and including a peripheral pad portion;
an upper substrate disposed on the peripheral circuit structure;
a stack structure disposed on the upper substrate, and including gate horizontal patterns, the gate horizontal patterns being stacked while being spaced apart from each other in a vertical direction perpendicular to an upper surface of the upper substrate;
a vertical channel structure passing through the stack structure in a first region on the upper substrate;
a vertical support structure passing through the stack structure in a second region on the upper substrate;
a separation structure passing through the stack structure in the first and second regions; and
a peripheral contact plug electrically connected to the peripheral pad portion,
wherein the stack structure has a stepped shape in the second region,
wherein an upper surface of the peripheral contact plug is at a higher level than an upper surface of the vertical channel structure,
wherein the vertical channel structure includes a lower channel portion, an upper channel portion on the lower channel portion, and an intermediate channel portion between the lower channel portion and the upper channel portion,
wherein the vertical support structure includes:
a lower support portion disposed at the same level as the lower channel portion;
an intermediate support portion disposed at the same level as the intermediate channel portion; and
an upper support portion disposed at the same level as the upper channel portion, and
wherein a side surface of the lower support portion, a side surface of the intermediate support portion and a side surface of the upper support portion are aligned with each other, and
wherein a side surface of the lower channel portion and a side surface of the upper channel portion are not aligned with each other.
18. The semiconductor device according to claim 17 ,
wherein the peripheral contact plug includes:
a lower plug portion disposed at the same level as the lower channel portion;
an intermediate plug portion disposed at the same level as the intermediate channel portion; and
an upper plug portion disposed at the same level as the upper channel portion, and
wherein a side surface of the lower plug portion, a side surface of the intermediate plug portion and a side surface of the upper plug portion are aligned with each other.
19. The semiconductor device according to claim 17 , wherein the stack structure includes a lower stack structure and an upper stack structure on the lower stack structure,
wherein the lower stack structure includes a plurality of lower gate horizontal patterns among the gate horizontal patterns,
wherein the upper stack structure includes a plurality of upper gate horizontal patterns among the gate horizontal patterns,
wherein the lower channel portion faces the plurality of lower gate horizontal patterns, and
wherein the upper channel portion faces the plurality of upper gate horizontal patterns.
20. The semiconductor device according to claim 17 , further comprising:
a bit line contact plug on and electrically connected to the vertical channel structure; and
a bit line on and electrically connected to the bit line contact plug,
wherein the gate horizontal patterns includes word lines, and
wherein the vertical channel structure includes:
an insulating core pattern;
a channel layer between the insulating core pattern and the gate horizontal patterns;
a pad pattern on the insulating core pattern and electrically connected to the channel layer; and
a data storage layer between the channel layer and the word lines, and
wherein the vertical support structure is electrically unconnected to the bit line.