Image sensor for improving linearity of analog-to-digital converter and image processing system including the same

1. An image sensor comprising:

a plurality of pixels;

a ramp generator configured to generate a ramp signal;

a plurality of analog-to-digital converters (ADCs) including a first ADC, a second ADC, a third ADC and a fourth ADC;

a first buffer including an input node configured to receive the ramp signal and a first output node connected to the first ADC and the second ADC;

a second buffer including the input node configured to receive the ramp signal and a second output node connected to the third ADC and the fourth ADC;

a first capacitor connected to the first ADC and the first buffer, a second capacitor connected to the second ADC and the first buffer, a third capacitor connected to the third ADC and the second buffer, and a fourth capacitor connected to the fourth ADC and the second buffer; and

a first counter connected to the first ADC, a second counter connected to the second ADC, a third counter connected to the third ADC, a fourth counter connected to the fourth ADC,

wherein the plurality of pixels have at least ten million pixels.

2. The image sensor of claim 1 , wherein each of the first and second buffers includes a current source and a transistor connected to the current source.

3. The image sensor of claim 2 , wherein the transistor is a p-type metal-oxide semiconductor (PMOS) transistor.

4. The image sensor of claim 2 , wherein the transistor is an n-type metal-oxide semiconductor (NMOS) transistor.

5. The image sensor of claim 3 , wherein the current source is located between the transistor and a power supply voltage.

6. The image sensor of claim 3 , wherein the current source is located between the transistor and a ground node.

7. The image sensor of claim 4 , wherein the current source is located between the transistor and a power supply voltage.

8. The image sensor of claim 4 , wherein the current source is located between the transistor and a ground node.

9. The image sensor of claim 2 , wherein an operation speed of each of the first to fourth counters is at least 1 GHz.

10. An image sensor comprising:

a plurality of pixels, each of the plurality of pixels being a 3T structure including a reset transistor connected to a floating diffusion, a driver transistor connected to the floating diffusion and a select transistor connected to the driver transistor;

a ramp generator configured to generate a ramp signal;

a first transistor, a second transistor, a third transistor, and a fourth transistor, each gate of the first to fourth transistors being configured to connect to the ramp generator;

a first analog-to-digital converter (ADC), a second ADC, a third ADC, and a fourth ADC, the first to fourth ADCs being configured to connect to the plurality of pixels;

a first capacitor connected to the first ADC and the first transistor, a second capacitor connected to the second ADC and the second transistor, a third capacitor connected to the third ADC and the third transistor, and a fourth capacitor connected to the fourth ADC and the fourth transistor; and

a first counter connected to the first ADC, a second counter connected to the second ADC, a third counter connected to the third ADC, a fourth counter connected to the fourth ADC,

wherein an operation speed of each of the first to fourth counters is at least 1 GHz.

11. The image sensor of claim 10 , wherein the first to fourth transistors are p-type metal-oxide semiconductor (PMOS) transistors.

12. The image sensor of claim 10 , wherein the first to fourth transistors are n-type metal-oxide semiconductor (NMOS) transistors.

13. The image sensor of claim 11 , wherein the first to fourth transistors are connected to a ground node.

14. The image sensor of claim 13 , further comprising a first current source connected to the first transistor, a second current source connected to the second transistor, a third current source connected to the third transistor and a fourth current source connected to the fourth transistor.

15. The image sensor of claim 14 , wherein the first transistor is located between the first current source and the ground node, the second transistor is located between the second current source and the ground node, the third transistor is located between the third current source and the ground node, and the fourth transistor is located between the fourth current source and the ground node.

16. The image sensor of claim 15 , wherein the plurality of pixels have at least ten million pixels.

17. The image sensor of claim 12 , wherein the plurality of pixels have at least ten million pixels.

18. An image sensor comprising:

a plurality of pixels, each of the plurality of pixels being a 5T structure including a photo transistor, a transfer transistor connected to the photo transistor, a reset transistor connected to a floating diffusion, a driver transistor connected to the floating diffusion and a select transistor connected to the driver transistor;

a ramp signal generator configured to generate a ramp signal;

a first analog-to-digital converter (ADC) and a second ADC, the first ADC being configured to receive the ramp signal and connected to a first buffer and the second ADC being configured to receive the ramp signal and connected to a second buffer different from the first buffer; and

a first counter connected to the first ADC and a second counter connected to the second ADC,

wherein an operation speed of each of the first to second counters is at least 1 GHz.

19. The image sensor of claim 18 , wherein each of the first and second buffers includes a current source and a transistor.

20. The image sensor of claim 19 , wherein the transistor is a p-type metal-oxide semiconductor (PMOS) transistor.