Image scaling
There is disclosed in one example a video processor, including: an input buffer to receive an input image; a slicer circuit to divide the input image into a plurality of N vertical slices; N parallel input buffers for de-rasterization; N parallel image scalers, wherein each scaler is hardware configured to scale in a raster form, one of the N vertical slices according to an image scaling algorithm; N parallel output buffers for rerasteriztion; and an output multiplexer to combine the scaled vertical slices into a combined scaled output image.
1. A video processor, comprising:
an input buffer to receive an input image;
a slicer circuit to divide the input image into a plurality of N vertical slices;
N parallel image scalers, wherein each scaler is hardware configured to linewise scale one of the N vertical slices according to an image scaling algorithm; and
an output multiplexer to combine the scaled vertical slices into a combined scaled output image.
2. The video processor of claim 1 , further comprising logic and circuitry to receive an input video stream, and to extract the input image from the input video stream.
3. The video processor of claim 1 , wherein each vertical slice is substantially a quartile of the input image.
4. The video processor of claim 1 , comprising logic and circuitry to receive an input video stream at a resolution selected from 480p, 480i, 720p, 720i, 1080p, 1080i, and 4K Ultra-High Definition (UHD), and to scale the input video stream to an output video stream at 8K UHD resolution via the N parallel image scalers.
5. The video processor of claim 1 , comprising logic and circuitry to receive an input video stream at 8K UHD resolution, and to downscale the image to a lower resolution via the N parallel image scalers.
6. The video processor of claim 1 , wherein the image scaling algorithm includes a linear interpolation.
7. The video processor of claim 1 , wherein the image scaling algorithm includes a higher order interpolation.
8. The video processor of claim 6 , wherein vertical slices representing substantially a first, second, and third quartile include three first pixels from a succeeding slice, and vertical slices representing second, third, and fourth quartiles include three last pixels from a preceding slice.
9. The video processor of claim 1 , wherein the N image scalers are pipelined.
10. The video processor of claim 1 , wherein the output image is a frame of a high-definition multimedia interface (HDMI)-compatible video stream.
11. The video processor of claim 9 , wherein the input image is a frame of a high-definition multimedia interface (HDMI)-compatible video stream.
12. An intellectual property (IP) block comprising the video processor of claim 1 .
13. A system-on-a-chip (SoC), comprising:
circuitry to receive an input image;
an image slicer to divide the input image into a plurality of N slices;
N image scalers disposed to scale the N slices in parallel, and including an interpolator circuit to interpolate intermediate pixels between pixels in the input image; and
an output multiplexer to multiplex scaled vertical slices into a combined scaled output image.
14. The SoC of claim 13 , further comprising N input de-rasterization buffers to receive the input image at 1/Nth of pixel rate; and a re-rasterization buffer to collect the N scaled slices and output them at a pixel rate of 1.
15. The SoC of claim 13 , wherein the interpolator circuit includes a higher order interpolator, and wherein at least some of the vertical slices include three last pixels from a preceding slice.
16. The SoC of claim 13 , further comprising:
a high-definition multimedia interface (HDMI) receiver to receive an input HDMI video stream;
a DSC decompressor to decompress the HDMI video input and to extract the input image;
a DSC compressor to receive the output image and to encode the output image into a scaled output HDMI video stream; and
an HDMI transmitter to transmit the scaled output HDMI video stream.
17. A method of scaling an image, comprising:
receiving an input image;
slicing the input image into a plurality of N slices;
raster-based scaling, in parallel, the N slices according to an image scaling algorithm; and
combining scaled vertical slices into a combined scaled output image.
18. The method of claim 17 , further comprising receiving extracting the input image from an input video stream.
19. The method of claim 17 , further comprising upscaling an image to 8K UHD resolution or downscaling the image from 8K UHD resolution.
20. The method of claim 19 , wherein the image scaling algorithm includes a quadratic interpolation, and wherein at least some of the vertical slices include one or more last pixels from a preceding slice.