Memory system and method of operating the same
A memory system includes: a nonvolatile memory device including a plurality of memory blocks and spare blocks; and a memory controller configured to control the nonvolatile memory device. The nonvolatile memory device may store spare information to any one block of the memory blocks or the spare blocks. When a bad block is detected from the memory blocks, the nonvolatile memory device replaces the bad block with any one of the spare blocks according to the spare information.
1. A memory system comprising:
a nonvolatile memory device including a plurality of planes each including memory blocks and spare blocks; and
a memory controller configured to control the nonvolatile memory device,
in response to a bad block being detected from the memory blocks, to replace the bad block with any one of the spare blocks according to spare information,
wherein the any one of the spare blocks is included in an identical plane with the bad block,
wherein the spare information includes a start queue address and an end queue address corresponding to the spare blocks included in each of the plurality of planes, and
wherein each of the plurality of planes includes a block to store the spare information.
2. The memory system according to claim 1 , wherein the nonvolatile memory device comprises:
peripheral circuits configured to perform various operations on the memory blocks or the spare blocks included in the plurality of planes; and
a control logic configured to control the peripheral circuits under control of the memory controller.
3. The memory system according to claim 2 ,
wherein, in response to the bad block being detected from the memory blocks, the control logic compares the start queue address and the end queue address included in the spare information,
wherein, in response to the start queue address and the end queue address not being identical with each other, the control logic replaces the bad block with a spare block corresponding to the start queue address, and
wherein, in response to the start queue address and the end queue address being identical with each other, the control logic processes a plane including the bad block as a bad plane.
4. The memory system according to claim 1 , wherein the spare information is updated in response to a status of the spare blocks.
5. The memory system according to claim 1 , wherein the start queue address is an address of the any one of the spare blocks.
6. The memory system according to claim 5 , wherein, in response to the any one of the spare blocks being replaced for the bad block, an address of a spare block corresponding to a subsequent turn is updated to be the start queue address.
7. The memory system according to claim 1 , wherein the end queue address is an address of a spare block corresponding to a last turn among the spare blocks.
8. The memory system according to claim 1 , wherein the spare blocks are normal blocks.
9. The memory system according to claim 1 , wherein the spare blocks are used only to replace the bad block.
10. A method of operating a memory system including memory blocks and spare blocks, the method comprising:
in response to a detection of a bad block among the memory blocks, reading spare information stored in a memory block among the memory blocks;
replacing the bad block with any one block of the spare blocks based on whether a start queue address is identical to an end queue address included in the spare information.
11. The method according to claim 10 , wherein the start queue address is set to an address of the any one block of the spare blocks.
12. The method according to claim 10 , comprising:
designating the any one block of the spare blocks as the start queue address;
wherein the any one block of the spare blocks designated as the start queue address is a block to be designated in a first turn as a replacement block among the spare blocks.
13. The method according to claim 10 , wherein, in response to the bad block being replaced with the any one block of the spare blocks, a spare block corresponding to a subsequent turn is designated as the start queue address.
14. The method according to claim 10 , wherein a block corresponding to a last turn among the spare blocks is designated as the end queue address.
15. The method according to claim 14 , comprising:
designating the any one block of the spare blocks as the start queue address;
replacing the bad block with the spare block corresponding to the start queue address in response to the start queue address and the end queue address being not identical with each other; and
processing a plane including the bad block to be a bad plane in response to the start queue address and the end queue address being identical with each other.
16. The method according to claim 10 , further comprising, after replacing the bad block with the any one block of the spare blocks, mapping an address of the bad block to an address of the replaced spare block.