Providing multiple low power link state wake-up options
Systems and devices can include a power management controller to determine a low power mode exit timing from a plurality of low power mode exit timing options, and cause the setting of a low power mode control register based on the determined low power mode exit timing. A message generator can generate a power mode request message. The power mode request message indicating the determined low power mode exiting timing. The power mode request message can be transmitted to a host across a multilane link.
1. An apparatus comprising:
a power management controller to:
determine a low power mode exit timing from a plurality of low power mode exit timing options, and
cause the setting of a low power mode control register based on the determined low power mode exit timing; and
a message generator to generate a power mode request message, the power mode request message indicating the determined low power mode exiting timing;
the apparatus to transmit the power mode request message to a host across a multilane link;
the power management controller to:
receive a power mode capability read request from a host;
determine power capability information; and
transmit the power capability information to the host;
the apparatus further comprising a Vendor-Defined Message (VDM) generator and a VDM receiver;
the VDM receiver to:
receive a VDM message requesting power capability information, and
determine power capability information based on a power capability table;
the VDM generator to compose a VDM message comprising power mode capability read response indicating the power capabilities of the apparatus;
the apparatus to send the VDM message to the host.
2. The apparatus of claim 1 , wherein the message generator comprises a Vendor Defined Message (VDM) generator to generate a VDM message that includes the determined low power mode exiting timing.
3. The apparatus of claim 2 , further comprising a VDM receiver to:
receive a VDM response message from a connected host across the multilane link, and
determine that the VDM response message indicates that the host denies the request for the low power mode exiting timing;
the power management controller to determine a second low power mode exiting timing; and
the VDM generator to generate a second VDM message with the second low power mode exit timing.
4. The apparatus of claim 1 , wherein the message generator comprises a Latency Tolerance Reporting (LTR) message generator to generate an LTR message that includes the determined low power mode exiting timing.
5. The apparatus of claim 4 , wherein the LTR message comprises a latency scale field, wherein the latency scale field comprises encoding representing the determined low power mode exiting timing.
6. The apparatus of claim 1 , wherein the low power control register comprises an L1 power mode substates control 2 register, the power management controller to set a T_POWER_ON_SCALE and T_POWER_ON_VALUE bit to indicate the determined low power mode exiting timing.
7. The apparatus of claim 1 , further comprising a Tpower_on switch to set the low power mode control register based on the determined low power mode exit timing.
8. The apparatus of claim 1 , the power management controller to:
receive a configuration read message from the host requesting an indication of power capabilities of the apparatus;
determine the power capabilities from a vendor-specific extended capability (VSEC) registers; and
indicate the power capabilities to the host from the VSEC registers.
9. A method comprising:
determining a low power mode exit timing from a plurality of low power mode exit timing options,
setting of a low power mode control register based on the determined low power mode exit timing;
generating a power mode request message, the power mode request message indicating the determined low power mode exiting timing; and
transmitting the power mode request message to a host device across a multilane link;
the method further comprising:
receiving a power mode capability read request from a host;
determining power capability information; and
transmitting the power capability information to the host;
wherein:
receiving a power mode capability read request from a host comprises receiving a VDM message requesting power capability information,
determining power capability information comprises determining power capability information based on a power capability table;
the method further comprising:
composing a VDM message comprising power mode capability read response indicating the power capabilities of the apparatus; and
transmitting the VDM message to the host.
10. The method of claim 9 , wherein generating a power mode request message comprises generating a VDM message that includes the determined low power mode exiting timing.
11. The method of claim 10 , further comprising:
receiving a VDM response message from a connected host across the multilane link, and
determining that the VDM response message indicates that the host denies the request for the low power mode exiting timing;
determining a second low power mode exiting timing; and
generating a second VDM message with the second low power mode exit timing.
12. The method of claim 9 , wherein generating a power mode request message comprises generating a Latency Tolerance Reporting (LTR) message that includes the determined low power mode exiting timing.
13. The method of claim 12 , wherein the LTR message comprises a latency scale field, wherein the latency scale field comprises encoding representing the determined low power mode exiting timing.
14. The method of claim 9 , wherein the low power control register comprises an L1 power mode substates control 2 register, the method comprising setting a T_POWER_ON_SCALE and T_POWER_ON_VALUE bit to indicate the determined low power mode exiting timing.
15. The method of claim 9 , further comprising:
receiving a configuration read message from the host requesting an indication of power capabilities of the apparatus;
determining the power capabilities from a vendor-specific extended capability (VSEC) registers; and
indicating the power capabilities to the host from the VSEC registers.
16. A system comprising:
a host comprising a system power management unit implemented at least partially in hardware;
a device connected to the host across a multilane link, the device comprising:
a power management controller to:
determine a low power mode exit timing from a plurality of low power mode exit timing options,
cause the setting of a low power mode control register based on the determined low power mode exit timing; and
a message generator to generate a power mode request message, the power mode request message indicating the determined low power mode exiting timing;
the device to transmit the power mode request message to the system power management unit across the multilane link;
the device comprising a Vendor-Defined Message (VDM) generator and a VDM receiver;
the VDM receiver to:
receive a VDM message requesting power capability information, and
determine power capability information based on a power capability table;
the VDM generator to compose a VDM message comprising power mode capability read response indicating the power capabilities of the device;
the device to send the VDM message to the host.
17. The system of claim 16 , wherein the message generator comprises a Vendor Defined Message (VDM) generator to generate a VDM message that includes the determined low power mode exiting timing.
18. The system of claim 17 , the system power management unit to:
determine that the low power mode exiting timing determined by the device should not be used, and
composing a VDM message indicating that the host has denied the determined low power mode exiting timing;
the device further comprising a VDM receiver to:
receive a VDM response message from a connected host across the multilane link, and
determine that the VDM response message indicates that the host denies the request for the low power mode exiting timing;
the power management controller to determine a second low power mode exiting timing; and
the device comprising a VDM generator to generate a second VDM message with the second low power mode exit timing.
19. The system of claim 16 , wherein the message generator comprises a Latency Tolerance Reporting (LTR) message generator to generate an LTR message that includes the determined low power mode exiting timing.
20. The system of claim 19 , wherein the LTR message comprises a latency scale field, wherein the latency scale field comprises encoding representing the determined low power mode exiting timing.
21. The system of claim 16 , wherein the low power control register comprises an L1 power mode substates control 2 register, the power management controller to set a T_POWER_ON_SCALE and T_POWER_ON_VALUE bit to indicate the determined low power mode exiting timing.