Semiconductor package and manufacturing method thereof
A package structure including at least one semiconductor chip, an insulating encapsulant, a conductive frame, a supporting frame, a conductive layer and a redistribution layer is provided. The at least one semiconductor chip has an active surface and a backside surface opposite to the active surface. The insulating encapsulant is encapsulating the at least one semiconductor chip. The conductive frame is surrounding the insulating encapsulant. The supporting frame is surrounding the conductive frame. The conductive layer is disposed on the backside surface of the semiconductor chip. The redistribution layer is disposed on and electrically connected to the active surface of the semiconductor chip.
1. A package structure, comprising:
at least one semiconductor chip having an active surface and a backside surface opposite to the active surface;
an insulating encapsulant encapsulating the at least one semiconductor chip;
a conductive frame, having a conductive opening, wherein the semiconductor chip and the insulating encapsulant are disposed in the conductive opening, and the semiconductor chip and the insulating encapsulant are surrounded by the conductive frame;
a supporting frame, having a supporting opening, wherein the conductive frame is disposed in the supporting opening, and the conductive frame is surrounded by the supporting frame;
a conductive layer disposed on the backside surface of the semiconductor chip; and
a redistribution layer disposed on and electrically connected to the active surface of the semiconductor chip, wherein:
an orthographic projection of an outline of the conductive opening on a virtual plane of the backside surface is a closed contour; and
an orthographic projection of an outline of the supporting opening on a virtual plane of the backside surface is a closed contour,
wherein the conductive frame is electrically connected to the conductive layer and the redistribution layer,
wherein the conductive layer covers the backside surface of the semiconductor chip, a backside surface of the supporting frame, a backside surface of the conductive frame, and the insulating encapsulant.
2. The package structure according to claim 1 , wherein a coefficient of thermal expansion of the supporting frame is lower than a coefficient of thermal expansion of the insulating encapsulant.
3. The package structure according to claim 1 , wherein the orthographic projection of the outline of the conductive opening on a virtual plane of the backside surface substantially corresponds to the orthographic projection of the outline of the supporting opening of the on a virtual plane of the backside surface.
4. The package structure according to claim 1 , wherein the package structure comprises two or more semiconductor chips, and the semiconductor chips are separated from one another by the supporting frame and the conductive frame.
5. The package structure according to claim 1 , wherein the insulating encapsulant is not revealed from the package structure.
6. The package structure according to claim 1 , wherein a material of the supporting frame comprises silicon, silicon carbide, aluminum oxide, beryllium oxide, or gallium nitride.
7. The package structure according to claim 1 , further comprising a plurality of conductive balls disposed on the redistribution layer, wherein the conductive balls are electrically connected to the semiconductor chip through the redistribution layer.
8. A manufacturing method of a package structure, comprising:
providing a carrier;
disposing a supporting frame and a conductive frame on the carrier, wherein the supporting frame has a plurality of supporting openings, the conductive frame has a conductive opening, and the conductive frame is located in each of the supporting openings to cover sidewalls of the supporting openings, wherein:
the conductive frame is surrounded by the supporting frame;
an orthographic projection of an outline of the conductive opening on a virtual plane of the backside surface is a closed contour; and
an orthographic projection of an outline of the supporting opening on a virtual plane of the backside surface is a closed contour;
bonding at least one semiconductor chip on the carrier and in the conductive opening of the conductive frame, wherein the semiconductor chip has an active surface and a backside surface opposite to the active surface;
forming an insulating encapsulant encapsulating the semiconductor chip, and filling the conductive opening of the conductive frame, wherein the semiconductor chip and the insulating encapsulant are disposed in the conductive opening, and the semiconductor chip and the insulating encapsulant are surrounded by the conductive frame;
forming a redistribution layer on the active surface of the semiconductor chip and on the insulating encapsulant, wherein the redistribution layer is electrically connected to the semiconductor chip;
de-bonding the carrier; and
forming a conductive layer on the backside surface of the semiconductor chip, and on the insulating encapsulant and the supporting frame,
wherein the conductive frame is electrically connected to the conductive layer and the redistribution layer,
wherein the conductive layer is formed to cover the backside surface of the semiconductor chip, a backside surface of the supporting frame, a backside surface of the conductive frame, and the insulating encapsulant.
9. The method according to claim 8 , wherein the supporting frame is pre-formed by the following steps before it is disposed on the carrier:
providing a supporting base; and
patterning the supporting base to form the supporting frame having the plurality of supporting openings, wherein each of the supporting openings penetrate through the supporting frame.
10. The method according to claim 9 , wherein the conductive frame is pre-formed by the following steps before it is disposed on the carrier:
placing a pattered mask on the supporting frame; and
forming the conductive frame in the plurality of supporting openings of the supporting frame through sputtering by using the patterned mask.
11. The method according to claim 8 , wherein two or more semiconductor chips are bonded on the carrier and in the supporting openings of the supporting frame, and the semiconductor chips are separated from each other by the supporting frame and the conductive frame.
12. The method according to claim 8 , wherein a coefficient of thermal expansion of the supporting frame is lower than a coefficient of thermal expansion of the insulating encapsulant.
13. The method according to claim 8 , further comprising:
disposing a plurality of conductive balls on the redistribution layer, wherein the plurality of conductive balls is electrically connected to the semiconductor chip through the redistribution layer.