Semiconductor device with bit lines at different levels and method for fabricating the same
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate having an upper surface; a plurality of first bit line contacts contacting the upper surface of the substrate and a plurality of second bit line contacts contacting the upper surface of the substrate, wherein the plurality of first bit line contacts and the plurality of second bit line contacts are positioned at different levels along a first direction; an air gap disposed between the first bit line contact and the second bit line contact; a plurality of first bit lines respectively correspondingly positioned on the plurality of first bit line contacts; and a plurality of second bit lines respectively correspondingly positioned on the plurality of first bit line contacts. The top surfaces of the plurality of second bit line contacts and the top surfaces of the plurality of first bit lines are positioned at different levels along a second direction substantially perpendicular to the first direction.
1. A semiconductor device, comprising:
a substrate having an upper surface;
a plurality of first bit line contacts contacting the upper surface of the substrate and a plurality of second bit line contacts contacting the upper surface of the substrate, wherein the plurality of first bit line contacts and the plurality of second bit line contacts are positioned at different levels along a first direction;
a plurality of first bit lines respectively correspondingly positioned on the plurality of first bit line contacts;
a plurality of second bit lines respectively correspondingly positioned on the plurality of first bit line contacts; and
wherein top surfaces of the plurality of second bit line contacts and top surfaces of the plurality of first bit lines are positioned at different levels along a second direction substantially perpendicular to the first direction.
2. The semiconductor device of claim 1 , further comprising an air gap disposed between the first bit line contact and the second bit line.
3. The semiconductor device of claim 2 , further comprising a nitride spacer disposed between the second bit line contact and the air gap.
4. The semiconductor device of claim 2 , wherein the air gap has a spacer shape.
5. The semiconductor device of claim 1 , wherein the second bit line contact has an upper width and a bottom width less than the upper width.
6. The semiconductor device of claim 1 , wherein the plurality of first bit lines are separated from each other and parallel to each other.
7. The semiconductor device of claim 6 , wherein the plurality of second bit lines are positioned between adjacent pairs of the plurality of first bit lines.
8. The semiconductor device of claim 1 , wherein the second bit line has an upper width and a bottom width less than the upper width.
9. The semiconductor device of claim 8 , wherein the second bit line contact has an upper width and a bottom width less than the upper width, and the bottom width of the second bit line is less than the upper width of the second bit line contact.
10. The semiconductor device of claim 1 , wherein bottom surfaces of the plurality of second bit lines are positioned at a vertical level higher than the top surfaces of the plurality of first bit lines.
11. A method for fabricating a semiconductor device, comprising:
providing a substrate having an upper surface;
forming a plurality of first bit line contacts contacting the upper surface of the substrate;
forming a plurality of first bit lines respectively correspondingly positioned on the plurality of first bit line contacts;
forming a plurality of second bit line contacts contacting the upper surface of the substrate, wherein the plurality of first bit line contacts and the plurality of second bit line contacts are positioned at different levels along a first direction; and
forming a plurality of second bit lines respectively correspondingly positioned on the plurality of first bit line contacts;
wherein top surfaces of the plurality of second bit line contacts and top surfaces of the plurality of first bit lines are positioned at different levels along a second direction substantially perpendicular to the first direction.
12. The method for fabricating the semiconductor device of claim 11 , further comprising: forming an air gap between the first bit line contact and the second bit line.
13. The method for fabricating the semiconductor device of claim 12 , comprising:
forming an opening to expose a center portion of an active area;
forming a first spacer in the opening and a second spacer covering the first spacer; and
removing the first spacer.
14. The method for fabricating the semiconductor device of claim 12 , further comprising: forming a nitride spacer between the second bit line contact and the air gap.
15. The method for fabricating the semiconductor device of claim 12 , wherein the air gap has a spacer shape.
16. The method for fabricating the semiconductor device of claim 12 , wherein after forming the second spacer, the opening has an upper width and a bottom width less than the upper width.
17. The method for fabricating the semiconductor device of claim 11 , wherein the second bit line contact has an upper width and a bottom width less than the upper width.
18. The method for fabricating the semiconductor device of claim 11 , wherein bottom surfaces of the plurality of second bit lines are positioned at a vertical level higher than the top surfaces of the plurality of first bit lines.
19. The method for fabricating the semiconductor device of claim 11 , wherein the plurality of first bit lines are separated from each other and parallel to each other.
20. The method for fabricating the semiconductor device of claim 11 , wherein the plurality of second bit lines are positioned between adjacent pairs of the plurality of first bit lines.