IP Library › Granted Patent US 10,979,074
Granted Patent B2
US 10,979,074 · App. 16/559,329 · Granted Apr 13, 2021

Low density parity check encoder having length of 16200 and code rate of 3/15, and low density parity check encoding method using the same

Inventors: Sung-Ik Park (Daejeon, KR); Heung-Mook Kim (Daejeon, KR); Sun-Hyoung Kwon (Daejeon, KR); Nam-Ho Hur (Sejong, KR)
Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
H03M13/1157H03M13/036H03M13/1165H03M13/1185H03M13/616H04L1/0041H04L1/0043H04L1/0057H04L1/0058H03M13/2792H03M13/6552H04L1/0071
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,979,074
App. No.
16/559,329
Granted
Apr 13, 2021
Kind
B2
Abstract

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

Claims (167)

1. A low density parity check (LDPC) decoder, comprising:

a receiving unit configured to receive a signal corresponding to an LDPC codeword having a length of 16200 and a code rate of 3/15, the LDPC codeword encoded using a sequence corresponding to a parity check matrix (PCM); and

a decoding unit configured to perform decoding the received signal, the decoding corresponding to the parity check matrix

wherein the sequence is represented by the following Sequence Table:

Sequence Table

 1st row: 8 372 841 4522 5253 7430 8542 9822 10550 11896 11988

 2nd row: 80 255 667 1511 3549 5239 5422 5497 7157 7854 11267

 3rd row: 257 406 792 2916 3072 3214 3638 4090 8175 8892 9003

 4th row: 80 150 346 1883 6838 7818 9482 10366 10514 11468 12341

 5th row: 32 100 978 3493 6751 7787 8496 10170 10318 10451 12561

 6th row: 504 803 856 2048 6775 7631 8110 8221 8371 9443 10990

 7th row: 152 283 696 1164 4514 4649 7260 7370 11925 11986 12092

 8th row: 127 1034 1044 1842 3184 3397 5931 7577 11898 12339 12689

 9th row: 107 513 979 3934 4374 4658 7286 7809 8830 10804 10893

10th row: 2045 2499 7197 8887 9420 9922 10132 10540 10816 11876

11st row: 2932 6241 7136 7835 8541 9403 9817 11679 12377 12810

12nd row: 2211 2288 3937 4310 5952 6597 9692 10445 11064 11272.

2. The LDPC decoder of claim 1 , wherein the LDPC codeword comprises a systematic part corresponding to the information bits and having a length of 3240, a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 1080, and a second parity part corresponding to an identity matrix included in the PCM and having a length of 11880.

3. The LDPC decoder of claim 2 , wherein the sequence has a number of rows equal to a sum of a value obtained by dividing a length of the systematic part, that is, 3240, by a circulant permutation matrix (CPM) size corresponding to the PCM, that is, 360, and a value obtained by dividing a length of the first parity part, that is, 1080, by the CPM size.

4. The LDPC decoder of claim 1 , wherein the LDPC codeword is generated by performing accumulation with respect to a memory and the accumulation is performed at parity bit addresses that are updated using the sequence.

5. The LDPC decoder of claim 4 , wherein the accumulation is performed while the rows of the sequence are being repeatedly changed by the CPM size of the PCM.

6. A low density parity check (LDPC) decoding method, comprising:

receiving a signal corresponding to an LDPC codeword having a length of 16200 and a code rate of 3/15, the LDPC codeword encoded using a sequence corresponding to a parity check matrix (PCM); and

decoding the received signal, the decoding corresponding to the parity check matrix,

wherein the sequence is represented by the following Sequence Table:

Sequence Table

 1st row:

8

372

841

4522

5253

7430

8542

9822

10550

11896

11988

 2nd row:

80

255

667

1511

3549

5239

5422

5497

7157

7854

11267

 3rd row:

257

406

792

2916

3072

3214

3638

4090

8175

8892

9003

 4th row:

80

150

346

1883

6838

7818

9482

10366

10514

11468

12341

 5th row:

32

100

978

3493

6751

7787

8496

10170

10318

10451

12561

 6th row:

504

803

856

2048

6775

7631

8110

8221

8371

9443

10990

 7th row:

152

283

696

1164

4514

4649

7260

7370

11925

11986

12092

 8th row:

127

1034

1044

1842

3184

3397

5931

7577

11898

12339

12689

 9th row:

107

513

979

3934

4374

4658

7286

7809

8830

10804

10893

10th row:

2045

2499

7197

8887

9420

9922

10132

10540

10816

11876

11st row:

2932

6241

7136

7835

8541

9403

9817

11679

12377

12810

12nd row:

2211

2288

3937

4310

5952

6597

9692

10445

11064

11272.

Priority Claims (2)
KR 10-2014-0106174 · Aug 14, 2014 · national
KR 10-2014-0120009 · Sep 11, 2014 · national
Continuity (3)
Continuation 15272142 · Sep 21, 2016
Continuation 14496356 · Sep 25, 2014
Related Publication 20190393891A1 · Dec 26, 2019