Shift register unit and method for driving the same, gate driving circuit and display apparatus

1. A gate driving circuit, comprising N stages of cascaded shift register units, wherein:

a clock signal terminal of an n th stage of shift register unit receives one of a first clock signal to an I th clock signal, an output signal terminal or a second output signal terminal of the n th stage of shift register unit is electrically connected to an input signal terminal of an (n+I/2) th stage of shift register unit, and a first reset signal terminal of the n th stage of shift register unit is electrically connected to an output signal terminal or a second output signal terminal of an (n+1+I/2) th stage of shift register unit, wherein N is an integer greater than or equal to 4, n is an integer greater than or equal to 1 and less than (N−I/2), and I is an even number;

wherein each of the shift register units comprises:

an input circuit electrically connected to an input signal terminal and a pull-up node of the shift register unit, and configured to transmit an input signal from the input signal terminal to the pull-up node;

an output circuit electrically connected to an output signal terminal, a clock signal terminal and the pull-up node, and configured to transmit a clock signal from the clock signal terminal to the output signal terminal under control of a voltage at the pull-up node;

a first reset circuit electrically connected to a first reset signal terminal, the pull-up node and a first level terminal, and configured to reset the pull-up node to a first level at the first level terminal under control of a first reset signal from the first reset signal terminal;

a first pull-down control circuit electrically connected to a first control signal terminal, the pull-up node, a first pull-down node of the shift register unit, the first level terminal, and the output signal terminal, and configured to control levels at the pull-up node and the output signal terminal using the first level at the first level terminal under control of a first control signal from the first control signal terminal; and

a first voltage control circuit electrically connected to a second control signal terminal, the first pull-down node and the first level terminal, and configured to control a voltage signal waveform at the first pull-down node using the first level at the first level terminal under control of a second control signal from the second control signal terminal.

2. The gate driving circuit according to claim 1 , wherein a second control signal terminal of the n th stage of shift register unit is electrically connected to an output signal terminal or a second output signal terminal of an (n+K) th stage of shift register unit, wherein K is an integer greater than or equal to 1 and less than or equal to I/2.

3. The gate driving circuit according to claim 1 , wherein the shift register unit further comprises:

a second voltage control circuit electrically connected to the input signal terminal, the first pull-down node, and the first level terminal, and configured to control the voltage signal waveform at the first pull-down node using the first level at the first level terminal under control of the input signal.

4. The gate driving circuit according to claim 1 , wherein the first voltage control circuit comprises a first transistor, and wherein:

a control electrode of the first transistor is electrically connected to the second control signal terminal, a first electrode of the first transistor is electrically connected to the first level terminal, and a second electrode of the first transistor is electrically connected to the first pull-down node.

5. The gate driving circuit according to claim 3 , wherein the second voltage control circuit comprises a second transistor, and wherein:

a control electrode of the second transistor is electrically connected to the input signal terminal, a first electrode of the second transistor is electrically connected to the first level terminal, and a second electrode of the second transistor is electrically connected to the first pull-down node.

6. The gate driving circuit according to claim 5 , further comprising:

a second pull-down control circuit electrically connected to a third control signal terminal, the pull-up node, a second pull-down node of the shift register unit, the first level terminal and the output signal terminal, and configured to control the levels at the pull-up node and the output signal terminal using the first level at the first level terminal under control of a third control signal from the third control signal terminal.

7. The gate driving circuit according to claim 6 , wherein the first voltage control circuit is further electrically connected to the second pull-down node, and is further configured to control a voltage signal waveform at the second pull-down node using the first level at the first level terminal under control of the second control signal.

8. The gate driving circuit according to claim 7 , wherein the first voltage control circuit further comprises a third transistor, and wherein:

a control electrode of the third transistor is electrically connected to the second control signal terminal, a first electrode of the third transistor is electrically connected to the first level terminal, and a second electrode of the third transistor is electrically connected to the second pull-down node.

9. The gate driving circuit according to claim 5 , further comprising:

a second pull-down control circuit electrically connected to a third control signal terminal, the pull-up node, a second pull-down node of the shift register unit, the first level terminal and the output signal terminal, and configured to control the levels at the pull-up node and the output signal terminal using the first level at the first level terminal under control of a third control signal from the third control signal terminal.

10. The gate driving circuit according to claim 9 , wherein the second voltage control circuit is further electrically connected to the second pull-down node, and is further configured to control a voltage signal waveform at the second pull-down node using the first level at the first level terminal under control of the input signal.

11. The gate driving circuit according to claim 10 , wherein the second voltage control circuit further comprises a fourth transistor, and wherein:

a control electrode of the fourth transistor is electrically connected to the input signal terminal, a first electrode of the fourth transistor is electrically connected to the first level terminal, and a second electrode of the fourth transistor is electrically connected to the second pull-down node.

12. The gate driving circuit according to claim 5 , wherein the output circuit comprises a fifth transistor and a first capacitor, and wherein:

a control electrode of the fifth transistor is electrically connected to the pull-up node, a first electrode of the fifth transistor is electrically connected to the clock signal terminal, and a second electrode of the fifth transistor is electrically connected to the output signal terminal; and

a first terminal of the first capacitor is electrically connected to the control electrode of the fifth transistor, and a second terminal of the first capacitor is electrically connected to the output signal terminal.

13. The gate driving circuit according to claim 12 , wherein the output circuit further comprises a sixth transistor, and wherein:

a control electrode of the sixth transistor is electrically connected to the pull-up node, a first electrode of the sixth transistor is electrically connected to the clock signal terminal, and a second electrode of the sixth transistor is electrically connected to the second output signal terminal.

14. The gate driving circuit according to claim 1 , wherein the shift register unit further comprises:

a second reset circuit electrically connected to a second reset signal terminal, the first level terminal, the pull-up node and the output signal terminal, and configured to reset the pull-up node and the output signal terminal to the first level at the first level terminal under control of a second reset signal from the second reset signal terminal.

15. A display apparatus, comprising a gate driving circuit, the gate driving circuit comprising N stages of cascaded shift register units, wherein:

a clock signal terminal of an n th stage of shift register unit receives one of a first clock signal to an I th clock signal, an output signal terminal or a second output signal terminal of the n th stage of shift register unit is electrically connected to an input signal terminal of an (n+I/2) th stage of shift register unit, and a first reset signal terminal of the n th stage of shift register unit is electrically connected to an output signal terminal or a second output signal terminal of an (n+1+I/2) th stage of shift register unit, wherein N is an integer greater than or equal to 4, n is an integer greater than or equal to 1 and less than (N−I/2), and I is an even number;

wherein each of the shift register units comprises:

an input circuit electrically connected to an input signal terminal and a pull-up node of the shift register unit, and configured to transmit an input signal from the input signal terminal to the pull-up node;

an output circuit electrically connected to an output signal terminal, a clock signal terminal and the pull-up node, and configured to transmit a clock signal from the clock signal terminal to the output signal terminal under control of a voltage at the pull-up node;

a first reset circuit electrically connected to a first reset signal terminal, the pull-up node and a first level terminal, and configured to reset the pull-up node to a first level at the first level terminal under control of a first reset signal from the first reset signal terminal;

a first pull-down control circuit electrically connected to a first control signal terminal, the pull-up node, a first pull-down node of the shift register unit, the first level terminal, and the output signal terminal, and configured to control levels at the pull-up node and the output signal terminal using the first level at the first level terminal under control of a first control signal from the first control signal terminal; and

a first voltage control circuit electrically connected to a second control signal terminal, the first pull-down node and the first level terminal, and configured to control a voltage signal waveform at the first pull-down node using the first level at the first level terminal under control of a second control signal from the second control signal terminal.

16. The display apparatus according to claim 15 , wherein a second control signal terminal of the n th stage of shift register unit is electrically connected to an output signal terminal or a second output signal terminal of an (n+K) th stage of shift register unit, wherein K is an integer greater than or equal to 1 and less than or equal to I/2.