Methods of forming microelectronic devices
A method of forming a microelectronic device comprises forming a spacer structure having a rectangular ring horizontal cross-sectional shape over a transistor, a portion of the spacer structure horizontally overlapping a drain region of the transistor. A masking structure is formed over the spacer structure and the transistor, the masking structure exhibiting an opening therein horizontally overlapping the drain region of the transistor and the portion of the spacer structure. A portion of an isolation structure overlying the drain region of the transistor is removed using the masking structure and the portion of the spacer structure as etching masks to form a trench vertically extending through the isolation structure to the drain region of the transistor. A drain contact structure is formed within the trench in the isolation structure. Microelectronic devices, memory devices, and electronic systems are also described.
1. A method of forming a microelectronic device, comprising:
forming a spacer structure having a rectangular ring horizontal cross-sectional shape over a transistor, a portion of the spacer structure horizontally overlapping a drain region of the transistor;
forming a masking structure over the spacer structure and the transistor, the masking structure exhibiting an opening therein horizontally overlapping the drain region of the transistor and the portion of the spacer structure;
removing a portion of an isolation structure overlying the drain region of the transistor using the masking structure and the portion of the spacer structure as etching masks to form a trench vertically extending through the isolation structure to the drain region of the transistor; and
forming a drain contact structure within the trench in the isolation structure.
2. The method of claim 1 , wherein forming a spacer structure comprises:
forming another masking structure over the transistor, the another masking structure exhibiting a rectangular opening therein horizontally overlapping the transistor;
forming a spacer material over surfaces inside and outside of the rectangular opening in the another masking structure; and
removing portions of the spacer material outside of the rectangular opening in the another masking structure and along a lower vertical boundary of the rectangular opening to form the spacer structure.
3. The method of claim 2 , further comprising removing remaining portions of the another masking structure after forming the spacer structure.
4. The method of claim 1 , wherein removing a portion of an isolation structure overlying the drain region comprises:
removing a portion of an additional masking structure vertically intervening between the isolation structure and each of the masking structure and the portion of the spacer structure using the masking structure and the portion of the spacer structure as etching masks to form a patterned additional masking structure exhibiting an additional opening within horizontal boundaries of the isolation structure; and
removing the portion of the isolation structure using the patterned additional masking structure as an etching mask to form the trench in the isolation structure.
5. The method of claim 1 , wherein forming a drain contact structure within the trench in the isolation structure comprises:
forming an electrically conductive material on surfaces inside and outside of the trench in the isolation structure; and
removing portions of the electrically conductive material outside of boundaries of trench in the isolation structure to form the drain contact structure.
6. The method of claim 1 , wherein forming a spacer structure further comprises forming the portion of the spacer structure to horizontally intervene between the drain region of the transistor and another drain region of another transistor horizontally neighboring the transistor.
7. The method of claim 6 , further comprising forming another portion of the spacer structure to horizontally intervene between an additional drain region of an additional transistor and a further drain region of a further transistor horizontally neighboring the additional transistor.
8. The method of claim 6 , wherein forming a masking structure comprises forming the opening in masking structure to horizontally overlap the drain region of the transistor, the portion of the spacer structure, and the another drain region of the another transistor.
9. The method of claim 8 , further comprising forming the masking structure to exhibit another opening therein horizontally overlapping a source region of the transistor.
10. The method of claim 8 , further comprising removing another portion of the isolation structure overlying the another drain region of the another transistor using the masking structure and the portion of the spacer structure as etching masks to form another trench vertically extending through the isolation structure to the another drain region of the another transistor, an additional portion of the isolation structure horizontally interposed between the trench in the isolation structure and the another trench in the isolation structure.
11. The method of claim 10 , further comprising forming another drain contact structure within the another trench in the isolation structure.
12. The method of claim 11 , wherein forming another drain contact structure comprises forming the drain contact structure and the another drain contact structure to exhibit substantially equal horizontal dimensions as one another and to be substantially horizontally aligned with one another.
13. The method of claim 1 , wherein forming a spacer structure further comprises forming the portion of the spacer structure to horizontally overlap a source region of the transistor and a gate structure of the transistor horizontally intervening between the source region of the transistor and the drain region of the transistor.
14. The method of claim 13 , wherein forming a masking structure comprises forming the opening in masking structure to horizontally overlap the source region of the transistor, the gate structure of the transistor, the drain region of the transistor, and the portion of the spacer structure.
15. The method of claim 14 , further comprising removing portion of another isolation structure overlying the source region of the transistor using the masking structure and the portion of the spacer structure as etching masks to form another trench vertically extending through the another isolation structure to the source region of the transistor.
16. The method of claim 15 , further comprising forming a source contact structure within the another trench in the another isolation structure.
17. The method of claim 16 , wherein forming a source contact structure comprises forming the source contact structure and the drain contact structure to exhibit substantially equal horizontal dimensions as one another and to be substantially horizontally aligned with one another.
18. A method, comprising:
forming a spacer structure in a ring shape over a transistor, the transistor comprising first and second conductively-doped regions and a gate structure over a channel region between the first and second conductively-doped regions, a portion of the spacer structure overlapping the first conductively-doped region;
forming a masking structure over the spacer structure and the transistor, the masking structure exhibiting an opening therein overlapping the first conductively-doped region and the portion of the spacer structure;
removing a portion of an isolation structure overlying the first conductively-doped region using the masking structure and the portion of the spacer structure as etching masks to form a trench exposing a part of the first conductively-doped region; and
forming a first contact structure in contact with the part of the first conductively-doped region through the trench.
19. The method of claim 18 , wherein forming a spacer structure comprises:
forming another masking structure over the transistor, the another masking structure exhibiting an opening therein overlapping the transistor;
forming a spacer material over surfaces inside and outside of the opening in the another masking structure; and
removing selected portions of the spacer material to form the spacer structure.
20. The method of claim 18 , wherein removing a portion of an isolation structure overlying the first conductively-doped region comprises:
removing a portion of an additional masking structure intervening between the isolation structure and each of the masking structure and the portion of the spacer structure using the masking structure and the portion of the spacer structure as etching masks to form a patterned additional masking structure exhibiting an additional opening; and
removing the portion of the isolation structure using the patterned additional masking structure as an etching mask to form the trench.
21. The method of claim 18 , wherein forming a spacer structure further comprises forming the portion of the spacer structure to horizontally overlap a second conductively-doped region and the gate structure.
22. The method of claim 21 , wherein forming a masking structure comprises forming the opening in the masking structure to overlap the second conductively-doped region, the gate structure, the first conductively-doped region, and the portion of the spacer structure.
23. The method of claim 22 , further comprising removing a portion of another isolation structure overlying the second conductively-doped region using the masking structure and the portion of the spacer structure as etching masks to form another trench exposing a part of the second conductively-doped region.
24. The method of claim 23 , further comprising forming a second contact structure in contact with the part of the second conductively-doped region through the another trench.
25. The method of claim 24 , wherein forming a second contact structure comprises forming the second contact structure and the first contact structure to exhibit substantially equal horizontal dimensions as one another and to be substantially horizontally aligned with one another.
26. The method of claim 18 , wherein the first conductively-doped region serves as a drain region and the second conductively-doped region serves as a source region.