Integrated circuit devices including vertical field-effect transistors

1. A standard cell comprising:

a first vertical field effect transistor (VFET) having a first conductivity type, wherein the first VFET comprises a first channel region protruding from a substrate in a vertical direction that is perpendicular to an upper surface of the substrate, and the first channel region has a first length in a first horizontal direction that is perpendicular to the vertical direction;

a second VFET having a second conductivity type that is different from the first conductivity type, wherein the second VFET comprises a second channel region protruding from the substrate in the vertical direction, and the second channel region has a second length in the first horizontal direction; and

a third VFET having the first conductivity type, wherein the third VFET comprises a third channel region protruding from the substrate in the vertical direction,

wherein the first channel region, the second channel region, and the third channel region are spaced apart from each other in the first horizontal direction and are sequentially arranged along the first horizontal direction, and

wherein the second length is greater than 1.5 times the first length.

2. The standard cell of claim 1 , wherein the third channel region has a third length in the first horizontal direction, and the third length is equal to the first length.

3. The standard cell of claim 1 , wherein the second length is greater than two times the first length.

4. The standard cell of claim 1 , further comprising a common gate layer that comprises a first portion comprising a first gate electrode of the first VFET, a second portion comprising a second gate electrode of the second VFET, and a third portion comprising a third gate electrode of the third VFET.

5. The standard cell of claim 1 , wherein the first VFET further comprises a first bottom source/drain region in the substrate, and the third VFET further comprises a third bottom source/drain region in the substrate, and

wherein the first bottom source/drain region and the third bottom source/drain region are configured to be connected to a first power having a first voltage.

6. The standard cell of claim 1 , further comprising:

a first bottom contact extending along a first cell boundary adjacent the first VFET; and

a second bottom contact extending along a second cell boundary adjacent the third VFET,

wherein the first bottom contact and the second bottom contact are spaced apart from each other in the first horizontal direction and extend longitudinally in a second horizontal direction that is perpendicular to the vertical direction and traverses the first horizontal direction, and

wherein the first bottom contact and the second bottom contact are configured to receive a first power having a first voltage.

7. The standard cell of claim 1 , wherein the standard cell comprises a first cell boundary adjacent the first VFET, a second cell boundary adjacent the third VFET, and the first cell boundary and the second cell boundary are spaced apart from each other in the first horizontal direction, and

wherein the second channel region comprises a portion that is equidistant from each of the first cell boundary and the second cell boundary in the first horizontal direction.

8. A standard cell comprising:

a first vertical field effect transistor (VFET) comprising a first channel region protruding from a substrate in a vertical direction that is perpendicular to an upper surface of the substrate;

a second VFET comprising a second channel region protruding from the substrate in the vertical direction; and

a third VFET comprising a third channel region protruding from the substrate in the vertical direction,

wherein the first channel region, the second channel region, and the third channel region are spaced apart from each other in a first horizontal direction that is perpendicular to the vertical direction and are sequentially arranged along the first horizontal direction,

wherein the standard cell comprises a first cell boundary adjacent the first VFET, a second cell boundary adjacent the third VFET, and the first cell boundary and the second cell boundary are spaced apart from each other in the first horizontal direction, and

wherein the second channel region comprises a portion that is equidistant from each of the first cell boundary and the second cell boundary in the first horizontal direction.

9. The standard cell of claim 8 , further comprising

a first bottom contact extending along the first cell boundary; and

a second bottom contact extending along the second cell boundary,

wherein the first bottom contact and the second bottom contact are configured to receive a first power having a first voltage.

10. The standard cell of claim 9 , wherein the first VFET further comprises a first bottom source/drain region in the substrate, and the third VFET further comprises a third bottom source/drain region in the substrate, and

wherein the first bottom contact is electrically connected to the first bottom source/drain region, and the second bottom contact is electrically connected to the third bottom source/drain region.

11. The standard cell of claim 9 , wherein the second VFET further comprises a second bottom source/drain region in the substrate, and a second top source/drain region on the second channel region,

wherein the standard cell further comprises a conductive line electrically connected to the second top source/drain region, and

wherein the second top source/drain region is configured to receive a second power having a second voltage that is different from the first voltage.

12. The standard cell of claim 8 , wherein the first channel region has a first length in the first horizontal direction, and the second channel region has a second length in the first horizontal direction, and

wherein the second length is greater than 1.5 times the first length.

13. The standard cell of claim 8 , further comprising a common gate layer that comprises a first portion comprising a first gate electrode of the first VFET, a second portion comprising a second gate electrode of the second VFET, and a third portion comprising a third gate electrode of the third VFET.

14. A standard cell comprising:

a first vertical field effect transistor (VFET) comprising a first channel region protruding from a substrate in a vertical direction that is perpendicular to an upper surface of the substrate;

a second VFET comprising a second channel region protruding from the substrate in the vertical direction;

a third VFET comprising a third channel region protruding from the substrate in the vertical direction, wherein the first channel region, the second channel region, and the third channel region are spaced apart from each other in a first horizontal direction that is perpendicular to the vertical direction and are sequentially arranged along the first horizontal direction;

a first bottom contact adjacent the first VFET, wherein the first bottom contact extends along a first cell boundary and is electrically connected to the first VFET; and

a second bottom contact adjacent the third VFET, wherein the second bottom contact extends along a second cell boundary and is electrically connected to the third VFET,

wherein the first cell boundary and the second cell boundary are spaced apart from each other in the first horizontal direction, and

wherein the first bottom contact and the second bottom contact are configured to receive a first power having a first voltage.

15. The standard cell of claim 14 , wherein the second VFET further comprises a second bottom source/drain region in the substrate, and a second top source/drain region on the second channel region,

wherein the standard cell further comprises a conductive line electrically connected to the second top source/drain region, and

wherein the second top source/drain region is configured to receive a second power having a second voltage that is different from the first voltage.

16. The standard cell of claim 14 , wherein the first VFET further comprises a first bottom source/drain region in the substrate, and the third VFET further comprises a third bottom source/drain region in the substrate, and

wherein the first bottom contact is electrically connected to the first bottom source/drain region, and the second bottom contact is electrically connected to the third bottom source/drain region.

17. The standard cell of claim 14 , wherein the first channel region has a first length in the first horizontal direction, and the second channel region has a second length in the first horizontal direction, and

wherein the second length is greater than 1.5 times the first length.

18. The standard cell of claim 17 , wherein the third channel region has a third length in the first horizontal direction, and the third length is equal to the first length.

19. The standard cell of claim 14 , further comprising a common gate layer that comprises a first portion comprising a first gate electrode of the first VFET, a second portion comprising a second gate electrode of the second VFET, and a third portion comprising a third gate electrode of the third VFET.

20. The standard cell of claim 19 , each of the first VFET and the third VFET has a first conductivity type, and the second VFET has a second conductivity type that is different from the first conductivity type.