Transistor, thin film transistor array panel, and related manufacturing method
A transistor may include a semiconductor, a source electrode, a drain electrode, and a gate electrode. The semiconductor may include a first doped region, a second doped region, a source region, a drain region, and a channel region. The channel region is positioned between the source region and the drain region. The first doped region is positioned between the channel region and the source region. The second doped region is positioned between the channel region and the drain region. A doping concentration of the first doped region is lower than a doping concentration of the source region. A doping concentration of the second doped region is lower than a doping concentration of the drain region. The source electrode is electrically connected to the source region. The drain electrode is electrically connected to the drain region. The gate electrode overlaps the channel region.
1. A transistor comprising:
a semiconductor, which comprises a first doped region, a second doped region, a source region, a drain region, and a channel region, wherein the channel region is positioned between the source region and the drain region, wherein the first doped region is positioned between the channel region and the source region, wherein the second doped region is positioned between the channel region and the drain region, wherein a doping concentration of the first doped region is lower than a doping concentration of the source region and is greater than 0, and wherein a doping concentration of the second doped region is lower than a doping concentration of the drain region and is greater than 0;
a source electrode, which is electrically connected to the source region;
a drain electrode, which is electrically connected to the drain region;
a first gate electrode, which overlaps the channel region; and
a passivation layer, which directly contacts the semiconductor,
wherein a first hole extends through the passivation layer and exposes the first doped region, and wherein a second hole extends through the passivation layer and exposes the second doped region.
2. The transistor of claim 1 comprising:
a substrate,
wherein the first gate electrode is positioned between the substrate and the semiconductor,
wherein a minimum distance between the substrate and the first doped region is greater than a minimum distance between the substrate and the source region.
3. The transistor of claim 1 comprising:
a substrate,
wherein the first gate electrode is positioned between the substrate and the semiconductor,
wherein a minimum distance between the substrate and the channel region is greater than a minimum distance between the substrate and the first doped region.
4. The transistor of claim 3 ,
wherein the first gate electrode directly contacts the substrate and is formed of polysilicon.
5. The transistor of claim 3 comprising:
a second gate electrode, wherein the channel region is positioned between the first gate electrode and the second gate electrode; and
a gate insulating layer, which is positioned between the channel region and the first gate electrode and directly contacts at least one of the first doped region and the second doped region.
6. The transistor of claim 1 comprising:
a gate insulating layer, which is positioned between the channel region and the first gate electrode and directly contacts at least one of the first doped region and the second doped region.
7. The transistor of claim 6 , wherein the gate insulating layer does not directly contact the source region and does not directly contact the drain region.
8. The transistor of claim 6 , wherein the gate insulating layer directly contacts each of the first doped region, the second doped region, and the channel region.
9. The transistor of claim 1 comprising:
a gate insulating layer, which is positioned between the channel region and the first gate electrode, wherein a face of the gate insulating layer directly contacts the first gate electrode; and
a passivation layer, which directly contacts the face of the gate insulating layer.
10. The transistor of claim 1 ,
wherein the first doped region includes a first portion contacting the channel region and a second portion contacting the source region, and
a thickness of the first portion of the first doped region is greater than a thickness of the second portion of the first doped region.
11. The transistor of claim 10 ,
wherein the second doped region includes a first portion contacting the channel region and a second portion contacting the drain region, and
a thickness of the first portion of the second doped region is greater than a thickness of the second portion of the second doped region.
12. The transistor of claim 1 , wherein the passivation layer directly contacts at least one of the source region and the drain region.
13. The transistor of claim 1 ,
wherein a first face of the channel region is positioned between the first gate electrode and a second face of the channel region,
wherein a first direction is perpendicular to the first face of the channel region, and
wherein a thickness of the first doped region in the first direction is less than a thickness of the source region in the first direction.