IP Library › Granted Patent US 10,990,013
Granted Patent B2
US 10,990,013 · App. 16/053,463 · Granted Apr 27, 2021

Method for forming semiconductor structure

Inventors: An-Ren Zi (Hsinchu, TW); Ching-Yu Chang (Yuansun village, TW); Chin-Hsiang Lin (Hsin-chu, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
G03F7/325G03F7/322G03F7/0047G03F7/025G03F7/027G03F7/038G03F7/091G03F7/094H01L21/0271H01L21/0274H01L21/0332H01L21/0337H01L21/266H01L21/3081H01L21/31144
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Quick Facts
Patent No.
US 10,990,013
App. No.
16/053,463
Granted
Apr 27, 2021
Kind
B2
Abstract

A method for forming a semiconductor device structure is provided. The method includes forming a material layer over a substrate and forming a resist layer over the material layer. The resist layer includes an inorganic material and an auxiliary. The inorganic material includes a plurality of metallic cores and a plurality of first linkers bonded to the metallic cores. The method includes exposing a portion of the resist layer. The resist layer includes an exposed region and an unexposed region. In the exposed region, the auxiliary reacts with the first linkers. The method also includes removing the unexposed region of the resist layer by using a developer to form a patterned resist layer. The developer includes a ketone-based solvent having a formula (a), wherein R 1 is linear or branched C 1 -C 5 alkyl, and R 2 is linear or branched C 3 -C 9 alkyl.

Claims (42)

1. A method for forming a semiconductor structure, comprising:

forming a material layer over a substrate;

forming a resist layer over the material layer, wherein the resist layer comprises an inorganic material and an auxiliary, the inorganic material comprises a plurality of metallic cores, and a plurality of first linkers bonded to the metallic cores;

exposing a portion of the resist layer, wherein the resist layer comprises an exposed region and an unexposed region, and in the exposed region, the auxiliary reacts with the first linkers;

removing the unexposed region of the resist layer by using a developer to form a patterned resist layer, wherein the developer comprises 3-heptanone, 6-methyl-3-heptanone, 5-methyl-3-heptanone, 4-methyl-3-heptanone, 6-ethyl-3-heptanone, 5-ethyl-3-heptanone, or 4-ethyl-3-heptanone.

2. The method for forming the semiconductor structure as claimed in claim 1 , wherein the developer further comprises water (H 2 O), and a ratio of water to the developer is in a range from about 0.01% to about 3%.

3. The method for forming the semiconductor structure as claimed in claim 1 , wherein the auxiliary comprises a plurality of second linkers, and the second linkers react with the first linkers during the exposure process to form a plurality of chemical bonds between the auxiliary and the inorganic material.

4. The method for forming the semiconductor structure as claimed in claim 1 , wherein the step of removing the unexposed region of the resist layer by using a developer is operated at a temperature in a range from about 15 degrees Celsius to about 25 degrees Celsius.

5. The method for forming the semiconductor structure as claimed in claim 1 , wherein the metallic cores comprise tin (Sn), indium (In), antimony (Sb) or a combination thereof.

6. The method for forming the semiconductor structure as claimed in claim 1 , wherein exposing the portion of the resist layer comprises:

irradiating the resist layer using a Krypton Fluoride (KrF) excimer laser, Argon Fluoride (ArF) excimer laser, Fluoride (F2) excimer laser, or Extreme ultra-violet (EUV) light.

7. A method for forming a semiconductor structure, comprising:

forming a material layer over a substrate;

forming a bottom layer over the material layer;

forming a middle layer over the bottom layer;

forming a resist layer over the middle layer, wherein the resist layer comprises an inorganic material and an auxiliary, the inorganic material comprises a plurality of first linkers bonded to a plurality of metallic cores, and the auxiliary comprises a plurality of second linkers;

exposing a portion of the resist layer by performing an exposure process, wherein the second linkers react with the first linkers during the exposure process;

removing a portion of the resist layer to form a patterned resist layer by using a ketone-based solvent, wherein the ketone-based solvent comprises 3-heptanone;

removing a portion of the middle layer by using the patterned resist layer as a mask to form a patterned middle layer; and

removing a portion of the bottom layer by using the patterned middle layer as a mask to form a patterned bottom layer.

8. The method for forming the semiconductor structure as claimed in claim 7 , further comprising:

forming a compound in an exposed region of the resist layer after exposing the portion of the resist layer, wherein the compound is made of the metallic cores, the second linkers and the first linkers, and the compound is not removed by the ketone-based solvent.

9. The method for forming the semiconductor structure as claimed in claim 7 , wherein exposing the portion of the resist layer comprises:

irradiating the resist layer using a Krypton Fluoride (KrF) excimer laser, Argon Fluoride (ArF) excimer laser, Fluoride (F2) excimer laser, or Extreme ultra-violet (EUV) light.

10. The method for forming the semiconductor structure as claimed in claim 7 , wherein the metallic cores comprise tin (Sn), indium (In), antimony (Sb) or a combination thereof.

11. A method for forming a semiconductor structure, comprising:

forming a material layer over a substrate;

forming a bottom layer over the material layer;

forming a middle layer over the bottom layer;

forming a resist layer over the middle layer, wherein the resist layer comprises an inorganic material and an auxiliary, and the inorganic material comprises a plurality of metallic cores and a plurality of first linkers bonded to the metallic cores, and the metallic cores comprise tin (Sn), indium (In), antimony (Sb), or a combination thereof;

exposing a portion of the resist layer by performing an exposure process; and

developing the resist layer to form a patterned resist layer by using a ketone-based solvent having a formula (a):

wherein R 1 is linear or branched C 1 -C 2 alkyl, and R 2 is linear or branched C 4 -C 9 alkyl.

12. The method for forming the semiconductor structure as claimed in claim 11 , wherein the auxiliary comprises a plurality of second linkers, and the second linkers react with the first linkers during the exposure process to form a plurality of chemical bonds between the auxiliary and the inorganic material.

13. The method for forming the semiconductor structure as claimed in claim 12 , wherein the first linkers of the inorganic material reacts with the second linkers of the auxiliary during the exposure process.

14. The method for forming the semiconductor structure as claimed in claim 11 , wherein a topmost surface of the middle layer is in direct contact with a bottommost surface of the resist layer.

15. The method for forming the semiconductor structure as claimed in claim 11 , wherein the developer comprises 3-heptanone, 2-octanone, 5-methyl-2-hexanone, or a combination thereof.

16. The method for forming the semiconductor structure as claimed in claim 11 , wherein the developer comprises 6-Methyl-2-heptanone, 5-Methyl-2-heptanone, 4-Methyl-2-heptanone, 3-Methyl-2-heptanone, 6-ethyl-2-heptanone, 5-ethyl-2-heptanone, 4-ethyl-2-heptanone, or 3-ethyl-2-heptanone.

17. The method for forming the semiconductor structure as claimed in claim 11 , wherein the developer comprises 3-heptanone, 6-methyl-3-heptanone, 5-methyl-3-heptanone, 4-methyl-3-heptanone, 6-ethyl-3-heptanone, 5-ethyl-3-heptanone, or 4-ethyl-3-heptanone.

18. The method for forming the semiconductor structure as claimed in claim 11 , wherein the developer comprises 4-heptanone, 3-methyl-4-heptanone, 2-methyl-4-heptanone, 3-ethyl-4-heptanone, or 2-ethyl-4-heptanone.

19. The method for forming the semiconductor structure as claimed in claim 11 , wherein the developer comprises 2-methyl-3-heptanone or 2-ethyl-3-heptanone.

20. The method for forming the semiconductor structure as claimed in claim 11 , wherein the bottom layer is made of a carbon backbone polymer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2018
From: ZI, AN-REN; CHANG, CHING-YU; LIN, CHIN-HSIANG
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 046900/0874 →
Continuity (3)
Provisional Application 62562070 · Sep 22, 2017
Provisional Application 62576782 · Oct 25, 2017
Related Publication 20190096675A1 · Mar 28, 2019