Low latency FIFO with auto sync
A method operates a first-in-first-out (FIFO) buffer with a first clock, and operates one of a read pointer or a write pointer of the FIFO buffer with the first clock while operating the other one of the read pointer or write pointer with a second clock. One of a serializer fed from the FIFO buffer output, or a de-serializer feeding the FIFO buffer input, is operated with the second clock. Timing pulses indicate that the pointer operating with the second clock has reached a predetermined point in its cycle. The phase of the second clock is adjusted based on a relationship between the timing pulses and an advance period of the pointer operating with the first clock. The pointer operating with the first clock is reset to achieve a desired value for the relationship. A skew created from adjusting the phase of the second clock is corrected.
1. A first-in-first-out (FIFO) buffer circuit for operating in two clock domains, comprising:
a parallel buffer with a write pointer cycling through the parallel buffer according to a first clock, a read pointer cycling through an output of the parallel buffer according to a second clock, and a pulse generation circuit generating timing pulses at a predetermined point of the read pointer's cycle;
a serializer circuit coupled to the output of the parallel buffer and operating with the second clock;
a clock phase adjustment circuit operable to adjust a phase of the second clock; and
a FIFO training logic circuit which receives the timing pulses from the pulse generation circuit and, based on a relationship between the timing pulses and an advance period of the write pointer, sends a control signal to the clock phase adjustment circuit to adjust the phase of the second clock, and sends a write pointer sync signal to reset the write pointer to achieve a desired value for the relationship, and then corrects a skew caused by adjusting the phase of the second clock.
2. The FIFO buffer circuit of claim 1 , wherein the FIFO training logic circuit measures the relationship between the timing pulses and an advanced period of the read pointer.
3. The FIFO buffer circuit of claim 2 , wherein the FIFO training logic circuit enters a training phase in which it repeatedly measures the relationship between the timing pulses and the advance period of the read pointer and repeatedly sends the control signal until a desired relationship is achieved.
4. The FIFO buffer circuit of claim 2 , wherein the FIFO training logic circuit enters a training phase in which it repeatedly measures the relationship between the timing pulses and the advance period of the write pointer and repeatedly sends the control signal until a range of second clock phase adjustments is determined, and then sends the control signal to adjust the second clock phase to a desired point in the range.
5. The FIFO buffer circuit of claim 2 , wherein the relationship is a predetermined count of the timing pulses within the advance period of the write pointer.
6. The FIFO buffer circuit of claim 1 , wherein the FIFO training logic circuit calculates an amount of phase shift required to correct the skew created from adjusting the phase of the second clock.
7. A first-in-first-out (FIFO) buffer circuit for operating in two clock domains, comprising:
a parallel buffer with a read pointer cycling through the parallel buffer according to a first clock, a write pointer cycling through an input of the parallel buffer according to a second clock, and a pulse generation circuit generating timing pulses at a predetermined point of the write pointer's cycle;
a de-serializer circuit coupled to the input of the parallel buffer and operating with the second clock;
a clock phase adjustment circuit operable to adjust a phase of the second clock; and
a FIFO training logic circuit which receives the timing pulses from the pulse generation circuit and, based on a relationship between the timing pulses and an advance period of the read pointer, sends a control signal to the clock phase adjustment circuit to adjust the phase of the second clock, and sends a read pointer sync signal to reset the read pointer to achieve a desired value for the relationship, and then corrects a skew caused by adjusting the phase of the second clock.
8. The FIFO buffer circuit of claim 7 , wherein the FIFO training logic circuit measures the relationship between the timing pulses and the advance period of the read pointer.
9. The FIFO buffer circuit of claim 8 , wherein the FIFO training logic circuit enters a training phase in which it repeatedly measures the relationship between the timing pulses and the advance period of the read pointer and repeatedly sends the control signal until a desired relationship is achieved.
10. The FIFO buffer circuit of claim 8 , wherein the FIFO training logic circuit enters a training phase in which it repeatedly measures the relationship between the timing pulses and the advance period of the read pointer, repeatedly sends the control signal until a range of second clock phase adjustments is determined, and then sends the control signal to adjust the second clock phase to a desired point in the range.
11. The FIFO buffer circuit of claim 8 , wherein the relationship is a predetermined count of the timing pulses within the advance period of the read pointer.
12. The FIFO buffer circuit of claim 7 , wherein the FIFO training logic circuit calculates an amount of phase shift required to correct the skew created from adjusting the phase of the second clock.
13. A method of operating a first-in-first-out (FIFO) buffer across two clock domains, comprising:
operating a FIFO buffer with a first clock;
operating one of a read pointer and a write pointer of the FIFO buffer with the first clock and operating the other one of the read pointer or write pointer with a second clock;
operating one of a serializer fed from an output of the FIFO buffer, and a de-serializer feeding an input of the FIFO buffer, with the second clock;
while operating the FIFO buffer, transmitting timing pulses indicating that the pointer operating with the second clock has reached a predetermined point in its cycle;
adjusting the phase of the second clock based on a relationship between the timing pulses and an advance period of the pointer operating with the first clock and resetting the pointer operating with the first clock to achieve a desired value for the relationship; and
correcting a skew created from adjusting the phase of the second clock.
14. The method of claim 13 , further comprising, at a FIFO training logic circuit, measuring the relationship between the timing pulses and the advance period and sending a control signal to a clock phase adjustment circuit to perform the phase adjustment of the second clock.
15. The method of claim 14 , further comprising placing the FIFO training logic circuit in a training state in which it repeatedly measures the relationship between the timing pulses and the advance period and repeatedly sends the control signal until a desired state of the relationship is achieved.
16. The method of claim 14 , further comprising placing the FIFO training logic circuit in a training state in which it repeatedly measures the relationship between the timing pulses and the advance period, repeatedly sends the control signal until a desired range of second clock phase adjustments is determined, and then sends the control signal to adjust the second clock phase to a desired point in the range.
17. The method of claim 13 , wherein the second clock operates meso-currently on an integer multiple frequency of the first clock.
18. The method of claim 13 , wherein the relationship is a predetermined count of the timing pulses occurring within a single instance of the advance period.
19. The method of claim 13 , wherein the relationship is a predetermined count of the timing pulses occurring within a designated fraction of the advance period.
20. The method of claim 13 , further comprising, prior to resetting the pointer operating with the first clock, calculating an amount of phase shift required to correct the skew created from adjusting the phase of the second clock.