Systems and methods for virtually partitioning a machine perception and dense algorithm integrated circuit
Systems and methods for virtually partitioning an integrated circuit may include identifying dimensional attributes of a target input dataset and selecting a data partitioning scheme from a plurality of distinct data partitioning schemes for the target input dataset based on the dimensional attributes of the target dataset and architectural attributes of an integrated circuit. The method may include disintegrating the target dataset into a plurality of distinct subsets of data based on the selected data partitioning scheme and identifying a virtual processing core partitioning scheme from a plurality of distinct processing core partitioning schemes for an architecture of the integrated circuit based on the disintegration of the target input dataset. The architecture of the integrated circuit may be virtually partitioned into a plurality of distinct partitions of processing cores and each of the plurality of distinct subsets of data may be mapped to one of the plurality of distinct partitions of processing cores.
1. A method for virtually partitioning an integrated circuit, the method comprising:
identifying a data partitioning scheme from a plurality of distinct data partitioning schemes for an input dataset based on:
(i) one or more dimensional attributes of the input dataset, and
(ii) one or more architectural attributes of the integrated circuit;
partitioning the input dataset into a plurality of distinct partitions of data based on the identified data partitioning scheme;
identifying a processing core partitioning scheme from a plurality of distinct processing core partitioning schemes for an architecture of the integrated circuit based on the partitioning of the input dataset; and
virtually partitioning the architecture of the integrated circuit based on (a) the data partitioning scheme and (b) the processing core partitioning scheme.
2. The method according to claim 1 , wherein
the identifying the processing core partitioning scheme includes referencing an array partitioning spectrum that includes multiple bands of distinct sizes of data partitions and associated optimal partitioning architectures for the integrated circuit.
3. The method according to claim 1 , wherein
virtually partitioning the architecture of the integrated circuit includes setting one or more virtual boundaries within a processing region of the integrated circuit that isolates one or more distinct subsets of processing cores of a multi-core array.
4. The method according to claim 1 , wherein:
the one or more dimensional attributes of the input dataset includes a width dimension and a height dimension of a segment or a layer of the input dataset; and
the identifying the data partitioning scheme is based on the width dimension and the height dimension of the segment or the layer of the input dataset.
5. The method according to claim 1 , wherein
identifying the processing core partitioning scheme is based at least on a number of the plurality of distinct partitions of data defined based on an application of the data partitioning scheme.
6. The method according to claim 1 , wherein
if a number of the plurality of distinct partitions of data satisfies or exceeds a first partitioning threshold, identifying the processing core partitioning scheme includes selecting a first virtual processing core partitioning scheme.
7. The method according to claim 6 , wherein
if the number of the plurality of distinct partitions of data satisfies or exceeds a second partitioning threshold, identifying the processing core partitioning scheme includes selecting only a second virtual processing core partitioning scheme having a greater number of virtual partitions than the first virtual processing core partitioning scheme.
8. The method according to claim 1 , further comprising:
identifying a size of the input dataset; and
assessing the size of the input dataset against a utilization threshold of the integrated circuit, wherein if the size of the input dataset does not satisfy the utilization threshold, automatically causing (a) the partitioning of the input dataset and (b) the virtual partitioning of the integrated circuit.
9. The method according to claim 1 , wherein the integrated circuit comprises:
(a) a plurality of distinct array processing cores, each array processing core of the plurality of distinct array processing cores comprising:
one or more data processing circuits; and
a register file; and
(b) a plurality of border cores, each border core of the plurality of border cores comprising:
at least one register file.
10. The method according to claim 1 , wherein
partitioning the input dataset into a plurality of distinct partitions of data includes:
setting one or more segmentation regions along a depth of the input dataset; and
subdividing the input dataset at each of the one or more segmentation regions along the depth of the input dataset.
11. The method according to claim 10 , wherein
setting the one or more segmentation regions includes:
identifying non-interactive adjacent segments of data along the depth of the input dataset; and
setting a segmentation region between the adjacent segments that do not interact.
12. The method according to claim 11 , wherein
non-interactive adjacent segments of data relate to segments of data that are neighboring along the depth of the input dataset and that can be processed by the integrated circuit independently of each other.
13. The method according to claim 10 , wherein
setting the one or more segmentation regions includes:
identifying non-interactive nonadjacent segments of data along the depth of the input dataset; and
setting a segmentation region between the nonadjacent segments that do not interact; and
non-interactive nonadjacent segments of data relate to segments of data that are spaced apart along the depth of the input dataset and that can be processed by the integrated circuit independently of each other.
14. The method according to claim 1 , wherein virtually partitioning the architecture of the integrated circuit includes:
defining two or more groupings of processing cores of a plurality of distinct processing cores; and
limiting an interaction between each of the two or more groupings of processing cores.
15. The method according to claim 14 , wherein
limiting the interaction between the two or more groupings of processing cores of the integrated circuit includes:
setting data movement instructions for each of the plurality of distinct partitions of data that restrict a movement of each respective distinct partition of data to movements within one distinct group of processing cores of the two or more groupings of processing cores.
16. The method according to claim 15 , wherein
the data movement instructions for each of the plurality of distinct partitions of data define a predetermined flow of each distinct partition of data from a memory into and out of a distinct grouping of processing cores.
17. The method according to claim 14 , wherein
limiting the interaction between the two or more groupings of processing cores includes:
restricting a movement of data between the two or more groupings of processing cores during one or more data processing sessions.
18. The method according to claim 1 , further comprising:
generating one or more predicate masks for one or more partitions of data of the plurality of distinct partitions of data, wherein the one or more predicate masks indicate that one or more portions of a given partition of data entering into a processing core of a given partition of a plurality of distinct partitions of processing cores is not valid.
19. The method according to claim 18 , wherein generating the one or more predicate masks includes:
evaluating a data propagation path of each of the plurality of distinct partitions of data; and
identifying one or more instances in which a movement of a given partition of data of the plurality of distinct partitions of data results in an invalid movement based on the evaluation.
20. The method according to claim 18 , wherein
each of the one or more predicate masks disables a processing at a given processing core of the integrated circuit of all or a portion of a given partition of data of the plurality of distinct partitions of data, or
each of the one or more predicate masks disables a part of a processing at a given processing core of the integrated circuit of all or a portion of a given partition of data of the plurality of distinct partitions of data.