IP Library › Granted Patent US 10,990,542
Granted Patent B2
US 10,990,542 · App. 16/425,812 · Granted Apr 27, 2021

Flash memory system and method of generating quantized signal thereof

Inventors: Hyunsu Ju (Seoul, KR); Gyosub Lee (Seoul, KR)
Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
G06F12/1475G06F3/0688G06F12/0246G06F12/1009G11C16/08G11C16/16G11C16/22G11C16/26G11C16/34
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Quick Facts
Patent No.
US 10,990,542
App. No.
16/425,812
Granted
Apr 27, 2021
Kind
B2
Abstract

The flash memory system according to the embodiment of the present invention is characterized by programming a selected page in a quantization signal generating operation, providing a reference read voltage to a selected word line connected to the selected page, A flash memory for generating a flash memory; And a memory controller for receiving a quantized signal from the flash memory and generating a response using the quantized signal, wherein the memory controller receives an challenge from a host and the flash memory performs the quantized signal generation.

Claims (42)

1. A flash memory system comprising:

a flash memory programming a selected page, providing a plurality of reference read voltages to a selected word line coupled to the selected page to generate a plurality of signals during a quantization signal generating operation, the plurality of signals corresponding to a plurality of quantization intervals, and generating a quantized signal by performing a logical operation on the plurality of signals; and

a memory controller receiving the quantized signal from the flash memory and generating a response using the quantized signal,

wherein the memory controller receives a challenge from a host and controls the flash memory to perform the quantization signal generating operation.

2. The flash memory system of claim 1 ,

wherein the selected page is programmed without a program verify operation.

3. The flash memory system of claim 2 ,

wherein the selected page is programmed with one program voltage or an increasing program voltage.

4. The flash memory system of claim 1 ,

wherein the plurality of reference read voltages are provided on the selected word line to separate into the plurality of quantization intervals.

5. The flash memory system of claim 4 ,

wherein the number of quantization intervals is greater than the number of program states.

6. The flash memory system of claim 1 ,

wherein the flash memory stores data for the quantized signal in some of the memory cells of the selected page.

7. The flash memory system of claim 6 ,

wherein the challenge includes combination order information for some of the memory cells.

8. The flash memory system of claim 7 ,

wherein the memory controller manages the combination order information for some memory cells using a map table of a flash translation layer.

9. The flash memory system of claim 1 ,

wherein the memory controller manages data information matched to a threshold voltage distribution state of the flash memory using a map table of a flash translation layer.

10. The flash memory system of claim 1 ,

wherein the memory controller receives the quantized signal from the flash memory and generates a quantized key.

11. The flash memory system of claim 1 , wherein the selected word line is coupled to a plurality of memory cells, and each of the plurality of signals has a plurality of values, each of the plurality of values indicating whether a threshold voltage of a corresponding one of the plurality of memory cells is in a corresponding one of the quantization intervals, and the flash memory performs an XOR operation on the plurality of signals to generate the quantized signal.

12. A flash memory system comprising:

a flash memory programming a memory block such that a threshold voltage distribution is grouped in units of subblocks, providing a plurality of reference read voltages to selected pages of selected subblocks during a quantization signal generating operation to generate a plurality of signals, the plurality of signals corresponding to a plurality of quantization intervals, respectively, and performing a logical operation on the plurality of signals to generate a quantized signal; and

a memory controller receiving the quantized signal from the flash memory and generating a response using the quantized signal,

wherein the memory controller receives a challenge from a host and controls the flash memory to perform the quantization signal generating operation.

13. The flash memory system of claim 12 ,

wherein the flash memory programs the memory block with the same data but applies the different program voltage for each subblock.

14. A method of generating a quantized signal of a flash memory system,

receiving a challenge from a host;

selecting a word line according to address information included in the challenge, and programming a selected page connected to the selected word line;

providing a plurality of reference read voltages to the selected word line to generate a plurality of signals, the plurality of signals corresponding to a plurality of quantization intervals, respectively; and

performing a logical operation on the plurality of signals to generate a quantized signal,

wherein the flash memory system generates a response using the quantized signal and provides the response to the host.

15. The method of claim 14 , wherein the program operation is performed without the program verify operation during the programming the selected page.

16. The method of claim 14 , wherein the selected page is programmed by one program voltage or an increasing program voltage.

17. The method of claim 14 , wherein the plurality of reference read voltages are provided on the selected word line to distinguish the plurality of quantization intervals.

18. The method of claim 14 , further comprising:

generating a quantized key using the quantized signal.

19. The method of claim 14 , wherein data for the quantized signal is stored in some of memory cells of the selected page.

20. The method of claim 19 , wherein the challenge includes address information for the selected page.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 30, 2019
From: JU, HYUNSU; LEE, GYOSUB
To: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
Reel/Frame 049318/0924 →
Priority Claims (1)
KR 10-2018-0082975 · Jul 17, 2018 · national
Continuity (1)
Related Publication 20200026666A1 · Jan 23, 2020