IP Library › Granted Patent US 10,991,695
Granted Patent B2
US 10,991,695 · App. 16/206,779 · Granted Apr 27, 2021

Method for manufacturing semiconductor device

Inventors: Chia-Yuan Chang (Hsinchu, TW); Xiong-Fei Yu (Hsinchu, TW); Hui-Cheng Chang (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L27/0924B82Y10/00H01L21/02532H01L21/02538H01L21/3115H01L21/8258H01L21/823807H01L29/068H01L29/0673H01L29/161H01L29/42392H01L29/4966H01L29/511H01L29/517H01L29/66439H01L29/66545H01L29/775H01L29/78696H01L21/823821H01L21/823828H01L29/20H01L29/66469H01L29/7848
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Quick Facts
Patent No.
US 10,991,695
App. No.
16/206,779
Granted
Apr 27, 2021
Kind
B2
Abstract

Disclosed is a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes forming a p-channel over a semiconductor substrate. A gate dielectric layer is formed over the p-channel. The gate dielectric layer is doped with a dopant. A first metal gate is formed over the gate dielectric layer.

Claims (42)

1. A method, comprising:

forming a p-channel over a semiconductor substrate;

forming a gate dielectric layer over the p-channel;

doping the gate dielectric layer over the p-channel with a dopant to form an oxide cap layer in contact with a top surface of the gate dielectric layer; and

forming a first metal gate electrode over and in contact with the oxide cap layer.

2. The method of claim 1 , wherein the dopant comprises lanthanum, yttrium, strontium, or combinations thereof.

3. The method of claim 1 , wherein the oxide cap layer comprises a rare earth compound, strontium, or combinations thereof.

4. The method of claim 1 , further comprising:

forming an n-channel over the semiconductor substrate,

wherein forming the gate dielectric layer is performed such that a portion of the gate dielectric layer is formed over the n-channel, and

wherein doping the gate dielectric layer is performed such that said portion of the gate dielectric layer over the n-channel is doped with the dopant.

5. The method of claim 4 , further comprising:

forming a second metal gate electrode over said portion of the gate dielectric layer over the n-channel, wherein the first metal gate electrode and the second metal gate electrode are made of the same material.

6. The method of claim 1 , wherein forming the gate dielectric layer is performed such that the gate dielectric layer is formed around the p-channel.

7. The method of claim 1 , wherein the first metal gate electrode comprises:

a p-work function metal layer in contact with the oxide cap layer; and

a first metal gate over the p-work function metal layer.

8. The method of claim 1 , wherein doping the gate dielectric layer is such that a dopant concentration of the oxide cap layer is higher than a dopant concentration of the gate dielectric layer.

9. A method, comprising:

forming an n-channel over a semiconductor substrate;

forming a gate dielectric layer over the n-channel;

doping the gate dielectric layer over the n-channel with a dopant to form an oxide cap layer in contact with a top surface of the gate dielectric layer;

forming a p-work function metal layer over the gate dielectric layer; and

forming a metal gate over and in contact with the p-work function metal layer.

10. The method of claim 9 , wherein the p-work function metal layer is formed such that the p-work function metal layer is in contact with the oxide cap layer.

11. A method, comprising:

forming an n-channel and a p-channel over a semiconductor substrate, wherein the n-channel and the p-channel are made of different materials;

forming an isolation structure between the n-channel and the p-channel;

forming a gate dielectric layer over the isolation structure, the n-channel, and the p-channel;

depositing a p-work function metal layer over the gate dielectric layer;

depositing a metal gate layer over the p-work function metal layer; and

removing portions of the metal gate layer, the p-work function metal layer, and the gate dielectric layer over the isolation structure to expose a top surface of the isolation structure, such that the gate dielectric layer is separated into a first gate dielectric layer over the n-channel and a second gate dielectric layer over the p-channel, the p-work function metal layer is separated into a first p-work function metal layer over the first gate dielectric layer and a second p-work function metal layer over the second gate dielectric layer, and the metal gate layer is separated into a first metal gate over the first p-work function metal layer and a second metal gate over the second p-work function metal layer.

12. The method of claim 11 , further comprising:

doping the gate dielectric layer with a dopant.

13. The method of claim 12 , wherein the dopant comprises lanthanum, yttrium, strontium, or combinations thereof.

14. The method of claim 12 , wherein doping the gate dielectric layer is performed such that a cap layer is formed in the gate dielectric layer.

15. The method of claim 14 , wherein the cap layer comprises a rare earth compound, strontium, or combinations thereof.

16. The method of claim 14 , wherein removing the portions of the metal gate layer, the p-work function metal layer, and the gate dielectric layer comprises removing a portion of the cap layer, such that the cap layer is separated into a first cap layer in the first gate dielectric layer and a second cap layer in the second gate dielectric layer.

17. The method of claim 11 , wherein the p-channel comprises germanium.

18. The method of claim 11 , wherein the gate dielectric layer comprises a high-k dielectric material.

19. The method of claim 11 , wherein forming the gate dielectric layer is performed such that the gate dielectric layer is formed over sidewalls and a top surface of the n-channel.

20. The method of claim 11 , wherein forming the gate dielectric layer is performed such that the gate dielectric layer is formed over sidewalls and a top surface of the p-channel.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 3, 2018
From: CHANG, CHIA-YUAN; YU, XIONG-FEI; CHANG, HUI-CHENG
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 047660/0770 →
Continuity (2)
Division 15000981 · Jan 19, 2016
Related Publication 20190115348A1 · Apr 18, 2019
Cited By (2)
US 12,262,558 US 12,376,361