Semiconductor memory devices
Semiconductor memory devices are provided. A semiconductor memory device includes an isolation layer in a first trench and a first gate electrode portion on the isolation layer. The semiconductor memory device includes a second gate electrode portion in a second trench. In some embodiments, the second gate electrode portion is wider, in a direction, than the first gate electrode portion. Moreover, in some embodiments, an upper region of the second trench is spaced apart from the first trench by a greater distance, in the direction, than a lower region of the second trench. Related methods of forming semiconductor memory devices are also provided.
1. A method of forming a semiconductor memory device, the method comprising:
forming a device isolation layer in a substrate to define active regions;
forming a trench to cross the active regions, the trench comprising first trench portions exposing the device isolation layer and second trench portions exposing the active regions; and
sequentially forming a gate insulating layer and a gate electrode layer in the trench,
wherein each of the second trench portions comprises an upper trench and a lower trench that is wider than the upper trench,
wherein the sequentially forming comprises forming the gate insulating layer in the upper trench to define gate regions in the lower trench, and
wherein the sequentially forming further comprises forming the gate electrode layer in the gate regions through the first trench portions.
2. The method of claim 1 , wherein the forming of the trench comprises:
performing an etching process on the substrate to form a preliminary trench;
forming a spacer on a side surface of the preliminary trench; and
isotropically etching portions of the active regions exposed by the spacer.
3. The method of claim 2 , wherein the forming of the trench further comprises selectively etching the device isolation layer to increase a width of the preliminary trench, before the forming of the spacer.
4. The method of claim 1 , further comprising removing a portion of the gate electrode layer by performing a first etching process to remove upper portions of the gate electrode layer in the first trench portions.
5. The method of claim 4 , wherein, during the first etching process, the gate insulating layer is on upper portions of the gate electrode layer in the gate regions.
6. The method of claim 4 , wherein the removing of the portion of the gate electrode layer further comprises performing a second etching process to remove upper portions of the gate electrode layer in the gate regions.
7. The method of claim 6 , further comprising forming semiconductor patterns in the gate regions, after the second etching process.
8. The method of claim 6 , further comprising forming a work-function adjusting layer, after the second etching process,
wherein the work-function adjusting layer extends into the gate regions.
9. The method of claim 8 , wherein the work-function adjusting layer comprises at least one of lanthanum (La), strontium (Sr), antimony (Sb), yttrium (Y), aluminum (Al), hafnium (Hf), or iridium (Ir).
10. The method of claim 1 , further comprising removing a portion of the gate electrode layer, wherein after the removing of the portion of the gate electrode layer, the method further comprises:
forming a metal oxide layer to contact the gate electrode layer, the metal oxide layer comprising a work-function adjusting material; and
performing a thermal treatment process to diffuse the work-function adjusting material from the metal oxide layer into the gate electrode layer.
11. A method of forming a semiconductor memory device, the method comprising:
forming a device isolation layer in a substrate to define active regions;
forming a trench to cross the active regions, the trench comprising first trench portions exposing the device isolation layer and second trench portions exposing the active regions;
sequentially forming a gate insulating layer and a gate electrode layer in the trench; and
removing a portion of the gate electrode layer by performing a first etching process to remove upper portions of the gate electrode layer in the first trench portions,
wherein each of the second trench portions comprises an upper trench and a lower trench that is wider than the upper trench,
wherein the sequentially forming comprises forming the gate insulating layer in the upper trench to define gate regions in the lower trench, and
wherein the sequentially forming further comprises forming the gate electrode layer in the gate regions through the first trench portions,
wherein the forming of the trench comprises:
performing an etching process on the substrate to form a preliminary trench;
forming a spacer on a side surface of the preliminary trench; and
isotropically etching portions of the active regions exposed by the spacer.
12. The method of claim 11 , wherein the forming of the trench further comprises selectively etching the device isolation layer to increase a width of the preliminary trench, before the forming of the spacer.