Semiconductor device and manufacturing method thereof

1. A semiconductor device comprising:

a substrate;

inter-device isolation structures over the substrate; and

a crown active region between the inter-device isolation structures, wherein the crown active region comprises:

a first semiconductor fin and a second semiconductor fin adjacent to the first semiconductor fin;

an intra-device isolation structure between the first semiconductor fin and the second semiconductor fin;

a source/drain structure comprising a first portion on the first semiconductor fin and comprising a second portion on the second semiconductor fin, wherein an air gap is between the intra-device isolation structure and the source/drain structure; and

a dielectric layer on the intra-device isolation structure, the dielectric layer physically contacting and extending continuously along an upper surface of the intra-device isolation structure from the first portion of the source/drain structure to the second portion of the source/drain structure, wherein upper surfaces of the inter-device isolation structures distal from the substrate and proximate to the crown active region are free of the dielectric layer.

2. The semiconductor device of claim 1 , wherein a first thickness of the intra-device isolation structure is smaller than a second thickness of the inter-device isolation structures.

3. The semiconductor device of claim 1 , wherein the first semiconductor fin and the second semiconductor fin are recessed below an upper surface of the intra-device isolation structure.

4. The semiconductor device of claim 1 , wherein the first portion of the source/drain structure and the second portion of the source/drain structure merge to form a continuous source/drain region.

5. The semiconductor device of claim 4 , wherein an upper surface of the continuous source/drain region facing away from the first semiconductor fin has at least one groove.

6. The semiconductor device of claim 1 , wherein the first portion of the source/drain structure is spaced apart from the second portion of the source/drain structure.

7. The semiconductor device of claim 1 , further comprising a gate structure over the first semiconductor fin and the second semiconductor fin.

8. The semiconductor device of claim 1 , wherein a thickness of the dielectric layer is greater than about 3 nm.

9. A semiconductor device comprising:

a substrate;

a crown structure protruding above the substrate, the crown structure comprising:

a plurality of fins;

an intra-device isolation structure between the plurality of fins;

source/drain regions over the plurality of fins; and

a dielectric layer over and in physical contact with the intra-device isolation structure, wherein the dielectric layer is between the plurality of fins; and

an inter-device isolation structure over the substrate and on opposing sides of the crow structure, wherein an upper surface of the inter-device isolation structure distal from the substrate is free of the dielectric layer.

10. The semiconductor device of claim 9 , wherein the source/drain regions comprise a first portion directly over a first fin of the plurality of fins, and comprise a second portion directly over a second fin of the plurality of fins.

11. The semiconductor device of claim 10 , wherein the dielectric layer extends continuously along an upper surface of the intra-device isolation structure from a first sidewall of the first portion of the source/drain regions to an opposing second sidewall of the second portion of the source/drain regions.

12. The semiconductor device of claim 10 , wherein the source/drain regions extend continuously from the first fin to the second fin.

13. The semiconductor device of claim 10 , wherein the first portion of the source/drain regions has a first peak, and the second portion of the source/drain regions has a second peak, wherein a pitch between the first peak and the second peak is substantially equal to a pitch between the first fin and the second fin.

14. The semiconductor device of claim 9 , wherein a lower surface of the intra-device isolation structure facing the substrate extends further from the substrate than a lower surface of the inter-device isolation structure facing the substrate.

15. The semiconductor device of claim 14 , wherein an upper surface of a first fin of the plurality of fins distal from the substrate is closer to the substrate than an upper surface of the intra-device isolation structure distal from the substrate.

16. A method for manufacturing a semiconductor device, the method comprising:

forming inter-device isolation structures over a substrate;

forming a crown structure between the inter-device isolation structures, the crown structure comprising semiconductor fins and an intra-device isolation structure between the semiconductor fins;

forming a gate structure over the semiconductor fins;

forming a dielectric layer over the crown structure and over the inter-device isolation structures, wherein the dielectric layer is formed to be in physical contact with the intra-device isolation structure and the inter-device isolation structures; and

recessing the semiconductor fins using an etching process, wherein the etching process removes the dielectric layer from the semiconductor fins and from the inter-device isolation structures, wherein after the etching process, the dielectric layer over the intra-device isolation structure remains, and upper surfaces of the inter-device isolation structures distal from the substrate are free of the dielectric layer.

17. The method of claim 16 , wherein recessing the semiconductor fins recesses upper surfaces of the semiconductor fins below an upper surface of the intra-device isolation structure.

18. The method of claim 16 , further comprising, after recessing the semiconductor fins, forming source/drain regions on the semiconductor fins.

19. The method of claim 18 , wherein the source/drain regions extend continuously over the semiconductor fins, wherein there is a void between the source/drain regions and the dielectric layer disposed over the intra-device isolation structure.

20. The method of claim 16 , wherein the etching process is a plasma etching process.