IP Library Granted Patent US 10,991,810
Granted Patent B2
US 10,991,810 · App. 17/008,633 · Granted Apr 27, 2021

Semiconductor device and method for fabricating the same

Inventors: Fu-Jung Chuang (Kaohsiung, TW); Tsuo-Wen Lu (Kaohsiung, TW); Chia-Ming Kuo (Kaohsiung, TW); Po-Jen Chuang (Kaohsiung, TW); Chi-Mao Hsu (Tainan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/6656H01L21/02164H01L21/02238H01L21/02255H01L29/66545H01L29/66795H01L29/785H01L21/31116
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Quick Facts
Patent No.
US 10,991,810
App. No.
17/008,633
Granted
Apr 27, 2021
Kind
B2
Abstract

A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate, forming a polymer block on a corner between the gate structure and the substrate, performing an oxidation process to form a first seal layer on sidewalls of the gate structure, and forming a source/drain region adjacent to two sides of the gate structure. Preferably, the polymer block includes fluorine, bromide, or silicon.

Claims (31)

1. A method for fabricating semiconductor device, comprising:

forming a gate structure on a substrate;

forming a polymer block on a corner between the gate structure and the substrate, wherein the polymer block comprises fluorine, bromide, or silicon;

performing an oxidation process to form a first seal layer on sidewalls of the gate structure; and

forming a source/drain region adjacent to two sides of the gate structure.

2. The method of claim 1 , further comprising forming the polymer block on a corner between sidewalls of the gate structure a top surface of the substrate.

3. The method of claim 1 , further comprising performing the oxidation process to oxidize sidewalls of the gate structure to form the first seal layer.

4. The method of claim 1 , further comprising forming the first seal layer on sidewalls of the gate structure and an inner sidewall of the polymer block.

5. The method of claim 1 , further comprising:

forming a gate material layer on the substrate;

forming a first hard mask on the gate material layer;

forming a second hard mask on the first hard mask; and

patterning the second hard mask, the first hard mask, and the gate material layer to form the gate structure and forming the polymer block.

6. The method of claim 1 , further comprising:

forming a second seal layer on sidewalls of the first seal layer and the polymer block;

removing the second seal layer and the first seal layer to form a first spacer and a second spacer;

forming the source/drain region adjacent to two sides of the second spacer;

forming an interlayer-dielectric (ILD) layer on the gate structure; and

performing a replacement metal gate (RMG) process to transform the gate structure into a metal gate.

7. The method of claim 6 , wherein sidewalls of the polymer block contact the first spacer and the second spacer.

8. A semiconductor device, comprising:

a gate structure on a substrate;

a first spacer on sidewalls of gate structure;

a polymer block adjacent to the first spacer and on a corner between the gate structure and the substrate, wherein the polymer block comprises fluorine, bromide, or silicon; and

a source/drain region adjacent to two sides of the first spacer.

9. The semiconductor device of claim 8 , further comprising a second spacer on sidewalls of the first spacer, wherein the polymer block is between the first spacer and the second spacer.

10. The semiconductor device of claim 9 , wherein the second spacer and the polymer block comprise different materials.

11. The semiconductor device of claim 8 , wherein the first spacer and the polymer block comprise different materials.

12. The semiconductor device of claim 8 , further comprising an interfacial layer under the polymer block.

13. The semiconductor device of claim 12 , wherein the polymer block is surrounded by the first spacer, the interfacial layer, and the second spacer.

14. The semiconductor device of claim 8 , wherein the polymer block is surrounded by the first spacer, the substrate, and the second spacer.

Priority Claims (1)
TW 108119452 · Jun 5, 2019 · national
Continuity (2)
Continuation 16503609 · Jul 4, 2019
Related Publication 20200403082A1 · Dec 24, 2020