Dynamic flip flop and electronic device

1. A dynamic flip-flop, having an input end and an output end, and comprising:

a transmission gate coupled to the input end and used to receive a first data signal, and output the first data signal to a first node according to a first clock signal and an inverted second clock signal thereof;

a first inverter coupled to the transmission gate via the first node, and used to invert the first data signal and output the inverted first data signal to a second node;

a second inverter coupled between the second node and the output end, and used to invert the inverted first data signal in order to generate a second data signal, and output the second data signal to the output end;

a pull-up transistor coupled between the second node and a power supply voltage, and used to pull up a voltage of the second node to the power supply voltage; and

a pull-down transistor coupled between the second node and a ground voltage, and used to pull down the voltage of the second node to the ground voltage;

wherein the transmission gate comprises a first N-type metal-oxide-semiconductor field-effect transistor and a first P-type metal-oxide-semiconductor field-effect transistor connected in parallel with each other, the drain of the first N-type MOS field-effect transistor and the drain of the first P-type MOS field-effect transistor are commonly coupled to the input end of the dynamic flip-flop via a third node, the source of the first N-type MOS field-effect transistor and the source of the first P-type MOS field-effect transistor are commonly coupled to the first node via a fourth node, the gate of the first N-type MOS field-effect transistor is used to receive the first clock signal, and the gate of the first P-type MOS field-effect transistor is used to receive the second clock signal;

wherein the first inverter is a tri-state inverter, and comprises a second P-type MOS field-effect transistor, a third P-type MOS field-effect transistor, a second N-type MOS field-effect transistor and a third N-type MOS field-effect transistor connected in series with each other, the source of the second P-type MOS field-effect transistor is coupled to the power supply voltage, the source of the third N-type MOS field-effect transistor is coupled to the ground voltage, the gate of the second P-type MOS field-effect transistor and the gate of the third N-type MOS field-effect transistor are respectively coupled to the first node for receiving the first data signal, the source of the third P-type MOS field-effect transistor is coupled to the drain of the second P-type MOS field-effect transistor, the source of the second N-type MOS field-effect transistor is coupled to the drain of the third N-type MOS field-effect transistor, the drain of the third P-type MOS field-effect transistor and the drain of the second N-type MOS field-effect transistor are commonly coupled to the second node via a fifth node, the gate of the third P-type MOS field-effect transistor is used to receive the first clock signal, and the gate of the second N-type MOS field-effect transistor is used to receive the second clock signal;

wherein the second inverter comprises a fourth P-type MOS field-effect transistor and a fourth N-type MOS field-effect transistor connected in series with each other, the source of the fourth P-type MOS field-effect transistor is coupled to the power supply voltage, the source of the fourth N-type MOS field-effect transistor is coupled to the ground voltage, the drain of the fourth P-type MOS field-effect transistor and the drain of the fourth N-type MOS field-effect transistor are commonly coupled to the output end of the dynamic flip-flop via a sixth node, and the gate of the fourth P-type MOS field-effect transistor and the gate of the fourth N-type MOS field-effect transistor are commonly coupled to the second node via a seventh node for receiving the inverted first data signal;

wherein the pull-up transistor is a fifth P-type MOS field-effect transistor, the pull-down transistor is a fifth N-type MOS field-effect transistor, the source of the fifth P-type MOS field-effect transistor is coupled to the power supply voltage, the source of the fifth N-type MOS field-effect transistor is coupled to the ground voltage, the drain of the fifth P-type MOS field-effect transistor and the drain of the fifth N-type MOS field-effect transistor are respectively coupled to the second node, and the gate of the fifth P-type MOS field-effect transistor and the gate of the fifth N-type MOS field-effect transistor are respectively coupled to the output end of the dynamic flip-flop for receiving the second data signal;

wherein the pull-up transistor and the pull-down transistor constitute a feedback inverter, and the feedback inverter is configured as a weak keeper circuit compared to the first inverter.

2. The dynamic flip-flop as claimed in claim 1 , further comprising a sixth P-type MOS field-effect transistor and a sixth N-type MOS field-effect transistor connected in series between the fifth P-type MOS field-effect transistor and the fifth N-type MOS field-effect transistor, the source of the sixth P-type MOS field-effect transistor is coupled to the drain of the fifth P-type MOS field-effect transistor, the source of the sixth N-type MOS field-effect transistor is coupled to the drain of the fifth N-type MOS field-effect transistor, the drain of the sixth P-type MOS field-effect transistor and the drain of the sixth N-type MOS field-effect transistor are respectively coupled to the second node, the gate of the sixth P-type MOS field-effect transistor is used to receive the second clock signal, and the gate of the sixth N-type MOS field-effect transistor is used to receive the first clock signal.

3. The dynamic flip-flop as claimed in claim 1 , further comprising a first transistor string and a second transistor string coupled between the input end and the third node.

4. The dynamic flip-flop as claimed in claim 3 , wherein the first transistor string comprises a seventh P-type MOS field-effect transistor and a seventh N-type MOS field-effect transistor connected in series with each other, the source of the seventh P-type MOS field-effect transistor and the source of the seventh N-type MOS field-effect transistor are respectively coupled to the input end for receiving the first data signal, the drain of the seventh P-type MOS field-effect transistor and the drain of the seventh N-type MOS field-effect transistor are commonly coupled to the third node via a first sub-node, the gate of the seventh P-type MOS field-effect transistor is used to receive a first scan enable signal, and the gate of the seventh N-type MOS field-effect transistor is used to receive a second scan enable signal that is an inversion of the first scan enable signal.

5. The dynamic flip-flop as claimed in claim 4 , wherein the second transistor string comprises an eighth P-type MOS field-effect transistor and an eighth N-type MOS field-effect transistor connected in series with each other, the source of the eighth P-type MOS field-effect transistor and the source of the eighth N-type MOS field-effect transistor are respectively coupled to a scanning end for receiving a scan signal, the drain of the eighth P-type MOS field-effect transistor and the drain of the eighth N-type MOS field-effect transistor are commonly coupled to the third node via a second sub-node, the gate of the eighth P-type MOS field-effect transistor is used to receive the second scan enable signal, and the gate of the eighth N-type MOS field-effect transistor is used to receive the first scan enable signal.

6. The dynamic flip-flop as claimed in claim 1 , further comprising:

a ninth P-type MOS field effect transistor coupled between the second node and the seventh node, wherein the source of the ninth P-type MOS field-effect transistor is coupled to the power supply voltage, the drain of the ninth P-type MOS field-effect transistor is coupled to a third sub-node between the second node and the seventh node, the gate of the ninth P-type MOS field-effect transistor is used to receive a reset signal; and

a ninth N-type MOS field-effect transistor connected in series between the third N-type MOS field-effect transistor and the ground voltage, wherein the source of the ninth N-type MOS field-effect transistor is coupled to the ground voltage, the drain of the ninth N-type MOS field-effect transistor is coupled to the source of the third N-type MOS field-effect transistor, and the gate of the ninth N-type MOS field-effect transistor is used to receive the reset signal.

7. The dynamic flip-flop as claimed in claim 1 , further comprising:

a tenth P-type MOS field-effect transistor connected in series between the power supply voltage and the second P-type MOS field-effect transistor, wherein the source of the tenth P-type MOS field-effect transistor is coupled to the power supply voltage, the drain of the tenth P-type MOS field-effect transistor is coupled to the source of the second P-type MOS field-effect transistor, the gate of the tenth P-type MOS field-effect transistor is used to receive a set signal; and

a tenth N-type MOS field-effect transistor coupled between the second node and the seventh node, wherein the source of the tenth N-type MOS field-effect transistor is coupled to the ground voltage, the drain of the tenth N-type MOS field-effect transistor is coupled to a third sub-node between the second node and the seventh node, and the gate of the tenth N-type MOS field-effect transistor is used to receive the set signal.

8. The dynamic flip-flop as claimed in claim 1 , further comprising:

an eleventh P-type MOS field-effect transistor connected in series between the power supply voltage and the second P-type MOS field-effect transistor, wherein the source of the eleventh P-type MOS field-effect transistor is coupled to the power supply voltage, the drain of the eleventh P-type MOS field-effect transistor is coupled to the source of the second P-type MOS field-effect transistor, the gate of the eleventh P-type MOS field-effect transistor is used to receive a first control signal;

an eleventh N-type MOS field-effect transistor connected in series between the third N-type MOS field-effect transistor and the ground voltage, wherein the source of the eleventh N-type MOS field-effect transistor is coupled to the ground voltage, the drain of the eleventh N-type MOS field-effect transistor is coupled to the source of the third N-type MOS field-effect transistor, the gate of the eleventh N-type MOS field-effect transistor is used to receive a second control signal that is an inversion of the first control signal;

a twelfth P-type MOS field-effect transistor connected in series between the fifth P-type MOS field-effect transistor and the second node, wherein the source of the twelfth P-type MOS field-effect transistor is coupled to the drain of the fifth P-type MOS field-effect transistor, the drain of the twelfth P-type MOS field-effect transistor is coupled to the second node, the gate of the twelfth P-type MOS field-effect transistor is used to receive the second control signal;

a twelfth N-type MOS field-effect transistor connected in series between the fifth N-type MOS field-effect transistor and the second node, wherein the source of the twelfth N-type MOS field-effect transistor is coupled to the drain of the fifth N-type MOS field-effect transistor, the drain of the twelfth N-type MOS field-effect transistor is coupled to the second node, the gate of the twelfth N-type MOS field-effect transistor is used to receive the first control signal;

a thirteen P-type MOS field-effect transistor, wherein the source of the thirteen P-type MOS field-effect transistor is coupled to a fourth sub-node between the drain of the fifth P-type MOS field-effect transistor and the source of the twelfth P-type MOS field-effect transistor, the drain of the thirteen P-type MOS field-effect transistor is coupled to a fifth sub-node between the second node and the fifth node, the gate of the thirteen P-type MOS field-effect transistor is used to receive the second clock signal; and

a thirteen N-type MOS field-effect transistor, wherein the source of the thirteen N-type MOS field-effect transistor is coupled to a sixth sub-node between the drain of the fifth N-type MOS field-effect transistor and the source of the twelfth N-type MOS field-effect transistor, the drain of the thirteen N-type MOS field-effect transistor is coupled to the fifth sub-node, and the gate of the thirteen N-type MOS field-effect transistor is used to receive the first clock signal.

9. An electronic device, comprising:

a dynamic flip-flop, having an input end and an output end, and including:

a transmission gate coupled to the input end and used to receive a first data signal, and output the first data signal to a first node according to a first clock signal and an inverted second clock signal thereof;

a first inverter coupled to the transmission gate via the first node, and used to invert the first data signal and output the inverted first data signal to a second node;

a second inverter coupled between the second node and the output end, and used to invert the inverted first data signal in order to generate a second data signal, and output the second data signal to the output end;

a pull-up transistor coupled between the second node and a power supply voltage, and used to pull up a voltage of the second node to the power supply voltage; and

a pull-down transistor coupled between the second node and a ground voltage, and used to pull down the voltage of the second node to the ground voltage;

wherein the transmission gate comprises a first N-type metal-oxide-semiconductor field-effect transistor and a first P-type metal-oxide-semiconductor field-effect transistor connected in parallel with each other, the drain of the first N-type MOS field-effect transistor and the drain of the first P-type MOS field-effect transistor are commonly coupled to the input end of the dynamic flip-flop via a third node, the source of the first N-type MOS field-effect transistor and the source of the first P-type MOS field-effect transistor are commonly coupled to the first node via a fourth node, the gate of the first N-type MOS field-effect transistor is used to receive the first clock signal, and the gate of the first P-type MOS field-effect transistor is used to receive the second clock signal;

wherein the first inverter is a tri-state inverter, and comprises a second P-type MOS field-effect transistor, a third P-type MOS field-effect transistor, a second N-type MOS field-effect transistor and a third N-type MOS field-effect transistor connected in series with each other, the source of the second P-type MOS field-effect transistor is coupled to the power supply voltage, the source of the third N-type MOS field-effect transistor is coupled to the ground voltage, the gate of the second P-type MOS field-effect transistor and the gate of the third N-type MOS field-effect transistor are respectively coupled to the first node for receiving the first data signal, the source of the third P-type MOS field-effect transistor is coupled to the drain of the second P-type MOS field-effect transistor, the source of the second N-type MOS field-effect transistor is coupled to the drain of the third N-type MOS field-effect transistor, the drain of the third P-type MOS field-effect transistor and the drain of the second N-type MOS field-effect transistor are commonly coupled to the second node via a fifth node, the gate of the third P-type MOS field-effect transistor is used to receive the first clock signal, and the gate of the second N-type MOS field-effect transistor is used to receive the second clock signal;

wherein the second inverter comprises a fourth P-type MOS field-effect transistor and a fourth N-type MOS field-effect transistor connected in series with each other, the source of the fourth P-type MOS field-effect transistor is coupled to the power supply voltage, the source of the fourth N-type MOS field-effect transistor is coupled to the ground voltage, the drain of the fourth P-type MOS field-effect transistor and the drain of the fourth N-type MOS field-effect transistor are commonly coupled to the output end of the dynamic flip-flop via a sixth node, and the gate of the fourth P-type MOS field-effect transistor and the gate of the fourth N-type MOS field-effect transistor are commonly coupled to the second node via a seventh node for receiving the inverted first data signal;

wherein the pull-up transistor is a fifth P-type MOS field-effect transistor, the pull-down transistor is a fifth N-type MOS field-effect transistor, the source of the fifth P-type MOS field-effect transistor is coupled to the power supply voltage, the source of the fifth N-type MOS field-effect transistor is coupled to the ground voltage, the drain of the fifth P-type MOS field-effect transistor and the drain of the fifth N-type MOS field-effect transistor are respectively coupled to the second node, and the gate of the fifth P-type MOS field-effect transistor and the gate of the fifth N-type MOS field-effect transistor are respectively coupled to the output end of the dynamic flip-flop for receiving the second data signal;

wherein the pull-up transistor and the pull-down transistor constitute a feedback inverter, and the feedback inverter is configured as a weak keeper circuit compared to the first inverter.

10. The electronic device as claimed in claim 9 , wherein the dynamic flip-flop further includes a sixth P-type MOS field-effect transistor and a sixth N-type MOS field-effect transistor connected in series between the fifth P-type MOS field-effect transistor and the fifth N-type MOS field-effect transistor, the source of the sixth P-type MOS field-effect transistor is coupled to the drain of the fifth P-type MOS field-effect transistor, the source of the sixth N-type MOS field-effect transistor is coupled to the drain of the fifth N-type MOS field-effect transistor, the drain of the sixth P-type MOS field-effect transistor and the drain of the sixth N-type MOS field-effect transistor are respectively coupled to the second node, the gate of the sixth P-type MOS field-effect transistor is used to receive the second clock signal, and the gate of the sixth N-type MOS field-effect transistor is used to receive the first clock signal.

11. The electronic device as claimed in claim 9 , wherein the dynamic flip-flop further includes a first transistor string and a second transistor string coupled between the input end and the third node.

12. The electronic device as claimed in claim 11 , wherein the first transistor string comprises a seventh P-type MOS field-effect transistor and a seventh N-type MOS field-effect transistor connected in series with each other, the source of the seventh P-type MOS field-effect transistor and the source of the seventh N-type MOS field-effect transistor are respectively coupled to the input end for receiving the first data signal, the drain of the seventh P-type MOS field-effect transistor and the drain of the seventh N-type MOS field-effect transistor are commonly coupled to the third node via a first sub-node, the gate of the seventh P-type MOS field-effect transistor is used to receive a first scan enable signal, and the gate of the seventh N-type MOS field-effect transistor is used to receive a second scan enable signal that is an inversion of the first scan enable signal.

13. The electronic device as claimed in claim 12 , wherein the second transistor string comprises an eighth P-type MOS field-effect transistor and an eighth N-type MOS field-effect transistor connected in series with each other, the source of the eighth P-type MOS field-effect transistor and the source of the eighth N-type MOS field-effect transistor are respectively coupled to a scanning end for receiving a scan signal, the drain of the eighth P-type MOS field-effect transistor and the drain of the eighth N-type MOS field-effect transistor are commonly coupled to the third node via a second sub-node, the gate of the eighth P-type MOS field-effect transistor is used to receive the second scan enable signal, and the gate of the eighth N-type MOS field-effect transistor is used to receive the first scan enable signal.

14. The electronic device as claimed in claim 9 , wherein the dynamic flip-flop further includes:

a ninth P-type MOS field effect transistor coupled between the second node and the seventh node, wherein the source of the ninth P-type MOS field-effect transistor is coupled to the power supply voltage, the drain of the ninth P-type MOS field-effect transistor is coupled to a third sub-node between the second node and the seventh node, the gate of the ninth P-type MOS field-effect transistor is used to receive a reset signal; and

a ninth N-type MOS field-effect transistor connected in series between the third N-type MOS field-effect transistor and the ground voltage, wherein the source of the ninth N-type MOS field-effect transistor is coupled to the ground voltage, the drain of the ninth N-type MOS field-effect transistor is coupled to the source of the third N-type MOS field-effect transistor, and the gate of the ninth N-type MOS field-effect transistor is used to receive the reset signal.

15. The electronic device as claimed in claim 9 , wherein the dynamic flip-flop further includes:

a tenth P-type MOS field-effect transistor connected in series between the power supply voltage and the second P-type MOS field-effect transistor, wherein the source of the tenth P-type MOS field-effect transistor is coupled to the power supply voltage, the drain of the tenth P-type MOS field-effect transistor is coupled to the source of the second P-type MOS field-effect transistor, the gate of the tenth P-type MOS field-effect transistor is used to receive a set signal; and

a tenth N-type MOS field-effect transistor coupled between the second node and the seventh node, wherein the source of the tenth N-type MOS field-effect transistor is coupled to the ground voltage, the drain of the tenth N-type MOS field-effect transistor is coupled to a third sub-node between the second node and the seventh node, and the gate of the tenth N-type MOS field-effect transistor is used to receive the set signal.

16. The electronic device as claimed in claim 9 , wherein the dynamic flip-flop further includes:

an eleventh P-type MOS field-effect transistor connected in series between the power supply voltage and the second P-type MOS field-effect transistor, wherein the source of the eleventh P-type MOS field-effect transistor is coupled to the power supply voltage, the drain of the eleventh P-type MOS field-effect transistor is coupled to the source of the second P-type MOS field-effect transistor, the gate of the eleventh P-type MOS field-effect transistor is used to receive a first control signal;

an eleventh N-type MOS field-effect transistor connected in series between the third N-type MOS field-effect transistor and the ground voltage, wherein the source of the eleventh N-type MOS field-effect transistor is coupled to the ground voltage, the drain of the eleventh N-type MOS field-effect transistor is coupled to the source of the third N-type MOS field-effect transistor, the gate of the eleventh N-type MOS field-effect transistor is used to receive a second control signal that is an inversion of the first control signal;

a twelfth P-type MOS field-effect transistor connected in series between the fifth P-type MOS field-effect transistor and the second node, wherein the source of the twelfth P-type MOS field-effect transistor is coupled to the drain of the fifth P-type MOS field-effect transistor, the drain of the twelfth P-type MOS field-effect transistor is coupled to the second node, the gate of the twelfth P-type MOS field-effect transistor is used to receive the second control signal;

a twelfth N-type MOS field-effect transistor connected in series between the fifth N-type MOS field-effect transistor and the second node, wherein the source of the twelfth N-type MOS field-effect transistor is coupled to the drain of the fifth N-type MOS field-effect transistor, the drain of the twelfth N-type MOS field-effect transistor is coupled to the second node, the gate of the twelfth N-type MOS field-effect transistor is used to receive the first control signal;

a thirteen P-type MOS field-effect transistor, wherein the source of the thirteen P-type MOS field-effect transistor is coupled to a fourth sub-node between the drain of the fifth P-type MOS field-effect transistor and the source of the twelfth P-type MOS field-effect transistor, the drain of the thirteen P-type MOS field-effect transistor is coupled to a fifth sub-node between the second node and the fifth node, the gate of the thirteen P-type MOS field-effect transistor is used to receive the second clock signal; and

a thirteen N-type MOS field-effect transistor, wherein the source of the thirteen N-type MOS field-effect transistor is coupled to a sixth sub-node between the drain of the fifth N-type MOS field-effect transistor and the source of the twelfth N-type MOS field-effect transistor, the drain of the thirteen N-type MOS field-effect transistor is coupled to the fifth sub-node, and the gate of the thirteen N-type MOS field-effect transistor is used to receive the first clock signal.