Systems and methods to test a memory device
View Patent ↗A memory device, includes: a memory array comprising a plurality of bit cells arranged along a plurality of rows and along a plurality of columns, respectively; and a control logic circuit coupled to the memory array, and configured to determine respective locations of a first plurality of diagonal bit cells of the memory array for testing one or more peripheral circuits coupled to the memory array, wherein the control logic circuit is further configured to determine respective locations of at least a second plurality of diagonal bit cells of the memory array for testing the one or more peripheral circuits, wherein a number of the plurality of rows is different than a number of the plurality of columns and the first plurality of diagonal bit cells span a first equal number of rows and columns and the second plurality of diagonal bit cells also span a second equal number of rows and columns.
1. A memory device, comprising:
a memory array comprising a plurality of bit cells arranged along a plurality of rows and along a plurality of columns, respectively; and
a control logic circuit coupled to the memory array, and configured to determine respective locations of a first plurality of diagonal bit cells of the memory array for testing one or more peripheral circuits coupled to the memory array,
wherein the control logic circuit is configured to determine the respective locations of the first plurality of diagonal bit cells further based on respective numbers of the plurality of rows and the plurality of columns and
when the number of the plurality of rows is larger than the number of the plurality of columns, the respective locations of the first plurality of diagonal bit cells span from a first row to a first intermediate row of the plurality of rows, and from a first column to a last column of the plurality of columns, wherein the first intermediate row is associated with a first row number equal to the number of the plurality of columns.
2. The device of claim 1 , wherein each of the plurality of bit cells comprises a write-once memory (WOM) bit cell.
3. The device of claim 1 , wherein the one or more peripheral circuits comprise a plurality of row circuits each configured to assert at least one of the plurality of rows, and a plurality of column circuits each configured to assert at least one of the plurality of columns.
4. The device of claim 1 , wherein in response to the respective locations of the first plurality of diagonal bit cells being determined, the control logic circuit is further configured to cause each of the first plurality of diagonal bit cells to be burned for testing the one or more peripheral circuits.
5. The device of claim 1 , wherein a number of the plurality of rows is different than a number of the plurality of columns and the first plurality of diagonal bit cells span an equal number of rows and columns.
6. The device of claim 1 , wherein when the number of the plurality of rows is equal to the number of the plurality of columns, the respective locations of the first plurality of diagonal bit cells span from a first row to a last row of the plurality of rows, and from a first column to a last column of the plurality of columns.
7. The device of claim 1 , wherein the control logic circuit is further configured to determine respective locations of at least a second plurality of diagonal bit cells of the memory array for testing the one or more peripheral circuits, and wherein the second plurality of diagonal bit cells span from the first row to a second intermediate row of the plurality of rows, and from the first column to the last column of the plurality of columns, wherein the second intermediate row is associated with a second row number greater than the number of the plurality of columns.
8. The device of claim 1 , wherein when the number of the plurality of rows is smaller than the number of the plurality of columns, the respective locations of the first plurality of diagonal bit cells span from a first row to a last row of the plurality of rows, and from a first column to a first intermediate column of the plurality of columns, wherein the first intermediate column is associated with a first column number equal to the number of the plurality of rows.
9. The device of claim 8 , wherein the control logic circuit is further configured to determine respective locations of at least a third plurality of diagonal bit cells of the memory array for testing the one or more peripheral circuits, and wherein the third plurality of diagonal bit cells span from the first row to the last row of the plurality of rows, and from the first column to second intermediate column of the plurality of columns, wherein the second intermediate column is associated with a second column number greater than the number of the plurality of rows.
10. A memory device, comprising:
a memory array comprising a plurality of bit cells arranged along a plurality of rows and along a plurality of columns, respectively;
a plurality of row circuits respectively arranged along the plurality of rows;
a plurality of column circuits respectively arranged along the plurality of columns; and
a control logic circuit coupled to the memory array, and configured to determine respective locations of a first plurality of diagonal bit cells of the memory array for testing the pluralities of the row and column circuits, wherein the control logic circuit is configured to determine the respective locations of the first plurality of diagonal bit cells further based on respective numbers of the plurality of rows and the plurality of columns, wherein a number of the plurality of rows is different than a number of the plurality of columns and the first plurality of diagonal bit cells span an equal number of rows and columns.
11. The device of claim 10 , wherein each of the plurality of bit cells comprises a write-once memory (WOM) bit cell.
12. The device of claim 10 , wherein each of the plurality of row circuits is configured to assert at least one of the plurality of rows, and each of the plurality of column circuits is configured to assert at least one of the plurality of columns.
13. The device of claim 10 , wherein in response to the respective locations of the first plurality of diagonal bit cells being determined, the control logic circuit is further configured to cause each of the first plurality of diagonal bit cells to be burned for testing the pluralities of the row and column circuits.
14. The device of claim 10 , wherein the control logic circuit includes a built-in self-test (BIST) circuit coupled to the plurality of row circuits and the plurality of column circuits to provide respective address information.
15. The device of claim 14 , wherein when the number of the plurality of rows is larger than the number of the plurality of columns, the respective locations of the first plurality of diagonal bit cells span from a first row to a first intermediate row of the plurality of rows, and from a first column to a last column of the plurality of columns, wherein the first intermediate row is associated with a first row number equal to the number of the plurality of columns.
16. The device of claim 15 , wherein the control logic circuit is further configured to determine respective locations of at least a second plurality of diagonal bit cells of the memory array for testing the pluralities of the row and column circuits, and wherein the second plurality of diagonal bit cells span from the first row to a second intermediate row of the plurality of rows, and from the first column to the last column of the plurality of columns, wherein the second intermediate row is associated with a second row number greater than the number of the plurality of columns.
17. The device of claim 14 , wherein when the number of the plurality of rows is smaller than the number of the plurality of columns, the respective locations of the first plurality of diagonal bit cells span from a first row to a last row of the plurality of rows, and from a first column to a first intermediate column of the plurality of columns, wherein the first intermediate column is associated with a first column number equal to the number of the plurality of rows.
18. A method, comprising:
providing a write-once memory array comprising a plurality of write-once bit cells arranged along a plurality of rows and along a plurality of columns, respectively;
determining respective locations of a first plurality of diagonal write-once bit cells of the write-once memory array based on respective numbers of the pluralities of rows and columns, wherein when the number of the plurality of rows is larger than the number of the plurality of columns, the respective locations of the first plurality of diagonal bit cells span from a first row to a first intermediate row of the plurality of rows, and from a first column to a last column of the plurality of columns, wherein the first intermediate row is associated with a first row number equal to the number of the plurality of columns; and
burning the first plurality of diagonal write-once bit cells for testing one or more peripheral circuits coupled to the write-once memory array.
19. The method of claim 18 , wherein a number of the plurality of rows is different than a number of the plurality of columns and the first plurality of diagonal write-once bit cells span an equal number of rows and columns.
20. The method of claim 18 , wherein when the number of the plurality of rows is equal to the number of the plurality of columns, the respective locations of the first plurality of diagonal bit cells span from a first row to a last row of the plurality of rows, and from a first column to a last column of the plurality of columns.