IP Library › Granted Patent US 10,998,229
Granted Patent B2
US 10,998,229 · App. 16/173,761 · Granted May 4, 2021

Transistor with improved self-aligned contact

Inventors: Kangguo Cheng (Schenectady, NY); Zhenxing Bi (Schenectady, NY); Juntao Li (Cohoes, NY); Dexin Kong (Guilderland, NY)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
H01L21/76897H01L21/31116H01L21/76802H01L21/76834H01L21/76877H01L21/823475H01L29/41725H01L29/4238H01L29/66568H01L29/665
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Quick Facts
Patent No.
US 10,998,229
App. No.
16/173,761
Granted
May 4, 2021
Kind
B2
Abstract

Systems, methods, and devices facilitating a transistor with an improved self-aligned contact are provided. In one example, a method comprises depositing a dielectric layer onto a first gate region and a second gate region of a semiconductor device, wherein the first gate region and the second gate region are separated by a substrate contact region, and wherein the dielectric layer has a first etch sensitivity to an inter-layer dielectric; and depositing a sacrificial layer onto the dielectric layer, wherein the sacrificial layer has a second etch sensitivity to the inter-layer dielectric that is greater than the first etch sensitivity.

Claims (18)

1. A semiconductor device, comprising:

a substrate;

a contact cap on a gate surface of the semiconductor device, wherein the contact cap extends from the gate surface to a first distance from the substrate of the semiconductor device;

a substrate contact on a non-gate surface of the semiconductor device, wherein the substrate contact extends from the substrate of the semiconductor device to a second distance from the substrate of the semiconductor device that is greater than the first distance; and

a second contact on the substrate contact, wherein the second contact encapsulates all portions of the substrate contact that extend beyond the first distance.

2. The semiconductor device of claim 1 , wherein the gate surface comprises a metal gate surface and at least one spacer surface.

3. The semiconductor device of claim 2 , wherein the metal gate surface extends further from the substrate of the semiconductor device than the at least one spacer surface.

4. The semiconductor device of claim 1 , further comprising:

an inter-level dielectric on at least a portion of the contact cap, the inter-level dielectric comprising a trench that defines an area of the second contact.

5. The semiconductor device of claim 4 , wherein the trench is formed into the inter-level dielectric at the area of the second contact by reactive-ion etching.

6. A semiconductor device comprising:

a substrate;

a gate region on the substrate that extends from the substrate to a first distance from the substrate;

a contact cap that extends from the gate region to a second distance from the substrate;

a substrate contact that is physically separate from the gate region, and adjacent to the gate region, wherein the substrate contact extends a third distance from the substrate that is longer that the second distance;

a contact liner that separates the substrate contact from the substrate and the gate regions; and

a second contact that encapsulates all portions of the substrate contact that extend beyond the second distance.

7. The semiconductor device of claim 6 , wherein the contact cap comprises silicon nitride.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 29, 2018
From: CHENG, KANGGUO; BI, ZHENXING; LI, JUNTAO; KONG, DEXIN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 047343/0231 →
Continuity (1)
Related Publication 20200135561A1 · Apr 30, 2020
Cited By (1)
US 12,284,821