IP Library › Granted Patent US 10,998,400
Granted Patent B2
US 10,998,400 · App. 16/555,291 · Granted May 4, 2021

Semiconductor device, inverter circuit, driving device, vehicle, and elevator

Inventor: Tatsuo Shimizu (Shinagawa, JP)
Assignee: Kabushiki Kaisha Toshiba
H01L29/063H01L29/0696H01L29/0856H01L29/0873H01L29/0878H01L29/1045H01L29/1608H01L29/4236H01L29/4238H01L29/66712H01L29/7802H01L29/7803H01L29/7813
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Quick Facts
Patent No.
US 10,998,400
App. No.
16/555,291
Granted
May 4, 2021
Kind
B2
Abstract

A semiconductor device includes a semiconductor layer having first and second planes; a first semiconductor region of a first conductivity type; second and third semiconductor regions of a second conductivity type between the first semiconductor region and the first plane; a fourth semiconductor region of a first conductivity type between the second semiconductor region and the first plane; a fifth semiconductor region of a first conductivity type between the third semiconductor region and the first plane; first and second trenches between the fourth and fifth semiconductor regions and over from the second to third semiconductor region; a sixth semiconductor region between the second and third semiconductor regions and between the first and second trenches; a seventh semiconductor region of a second conductivity type between the first trench and the first semiconductor region and contacting the second and third semiconductor regions; a first and second gate electrode in the trenches.

Claims (33)

1. A semiconductor device comprising:

a semiconductor layer having a first plane and a second plane facing the first plane;

a first semiconductor region of a first conductivity type existing in the semiconductor layer;

a second semiconductor region of a second conductivity type existing in the semiconductor layer and being located between the first semiconductor region and the first plane;

a third semiconductor region of a second conductivity type existing in the semiconductor layer and being located between the first semiconductor region and the first plane;

a fourth semiconductor region of a first conductivity type existing in the semiconductor layer and being located between the second semiconductor region and the first plane;

a fifth semiconductor region of a first conductivity type existing in the semiconductor layer and being located between the third semiconductor region and the first plane;

a first trench existing in the semiconductor layer and being located between the fourth semiconductor region and the fifth semiconductor region and over from the second semiconductor region to the third semiconductor region;

a second trench existing in the semiconductor layer and being located between the fourth semiconductor region and the fifth semiconductor region and over from the second semiconductor region to the third semiconductor region;

a sixth semiconductor region of a first conductivity type existing in the semiconductor layer, being located between the first semiconductor region and the first plane, and being located between the second semiconductor region and the third semiconductor region and between the first trench and the second trench;

a seventh semiconductor region of a second conductivity type existing in the semiconductor layer, being located between the first trench and the first semiconductor region, and being in contact with the second semiconductor region and the third semiconductor region;

an eighth semiconductor region of a second conductivity type existing in the semiconductor layer, being located between the second trench and the first semiconductor region, and being in contact with the second semiconductor region and the third semiconductor region;

a first gate electrode located in the first trench;

a second gate electrode located in the second trench;

a first gate insulating layer located between the first gate electrode and the second semiconductor region and between the first gate electrode and the third semiconductor region;

a second gate insulating layer located between the second gate electrode and the second semiconductor region and between the second gate electrode and the third semiconductor region;

a first electrode located on a side of the semiconductor layer closer to the first plane; and

a second electrode located on a side of the semiconductor layer closer to the second plane.

2. The semiconductor device according to claim 1 , wherein a first conductivity type impurity concentration of the sixth semiconductor region is higher than a first conductivity type impurity concentration of the first semiconductor region.

3. The semiconductor device according to claim 1 , wherein a second conductivity type impurity concentration of the seventh semiconductor region is higher than a second conductivity type impurity concentration of the second semiconductor region.

4. The semiconductor device according to claim 1 , wherein a distance between the first trench and the second plane is larger than a distance between the second semiconductor region and the second plane.

5. The semiconductor device according to claim 1 , wherein a distance between the first trench and the second plane is larger than a distance between the fourth semiconductor region and the second plane.

6. The semiconductor device according to claim 1 , further comprising a ninth semiconductor region of a first conductivity type being provided between the first semiconductor region and the second semiconductor region and having a first conductivity type impurity concentration higher than that of the first semiconductor region.

7. The semiconductor device according to claim 1 , further comprising a tenth semiconductor region of a first conductivity type being provided between the first semiconductor region and the sixth semiconductor region and having a first conductivity type impurity concentration higher than that of the first semiconductor region.

8. The semiconductor device according to claim 7 , wherein a first conductivity type impurity concentration of the sixth semiconductor region is higher than a first conductivity type impurity concentration of the tenth semiconductor region.

9. The semiconductor device according to claim 8 , further comprising an eleventh semiconductor region of a first conductivity type being provided between the tenth semiconductor region and the sixth semiconductor region and having a first conductivity type impurity concentration lower than that of the tenth semiconductor region.

10. The semiconductor device according to claim 9 , wherein the eleventh semiconductor region is located between the seventh semiconductor region and the eighth semiconductor region.

11. The semiconductor device according to claim 1 , wherein the semiconductor layer is a silicon carbide.

12. The semiconductor device according to claim 11 , wherein the seventh semiconductor region and the eighth semiconductor region contain aluminum and boron.

13. An inverter circuit comprising the semiconductor device according to claim 1 .

14. A driving device comprising the semiconductor device according to claim 1 .

15. A vehicle comprising the semiconductor device according to claim 1 .

16. An elevator comprising the semiconductor device according to claim 1 .

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 28, 2019
From: SHIMIZU, TATSUO
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 050838/0129 →
Priority Claims (1)
JP JP2019-050329 · Mar 18, 2019 · national
Continuity (1)
Related Publication 20200303494A1 · Sep 24, 2020
Cited By (1)
US 12,520,552