Auto calibration dead-time control circuit

1. A control circuit for controlling dead-time of a direct current to direct current (DC-DC) converter, the control circuit comprising:

a first transistor comprising a source/drain terminal coupled to an output voltage of the DC-DC converter configured to provide current based on the output voltage;

a digital up/down counter comprising an output terminal electrically coupled to an input terminal of a delay cell of the DC-DC converter;

a current sensing circuit electrically coupled to an input terminal of the digital up/down counter configured to receive the current and drive the digital up/down counter based on the current;

a second transistor electrically coupled to the current sensing circuit, a gate terminal of the second transistor is electrically coupled to a reference voltage; and

a capacitor electrically coupled between the current sensing circuit and the input terminal of the digital up/down counter.

2. The control circuit of claim 1 , wherein

the first transistor is configured to be operational based on a comparison between the output voltage and a gate voltage of the first transistor,

the current sensing circuit is further configured to either modify or maintain a count of the digital up/down counter, and

the digital up/down counter modifies or maintains a delay time of the delay cell to minimize or eliminate the dead-time of the DC-DC converter.

3. The control circuit of claim 1 , further comprising a switch electrically coupled in parallel with the capacitor.

4. The control circuit of claim 1 , wherein the current sensing circuit comprises:

a third transistor and a fourth transistor electrically coupled to each other via a gate terminal and a source/drain terminal of each transistor,

wherein the third transistor is electrically coupled between the second transistor and the fourth transistor via the gate terminal of the third transistor and a source/drain terminal of the second transistor.

5. The control circuit of claim 1 , wherein a gate terminal of the first transistor is electrically coupled to a reference voltage.

6. The control circuit of claim 1 , wherein the current sensing circuit comprises:

a third transistor and a fourth transistor cross coupled between the first transistor and the second transistor,

wherein:

a source/drain terminal of the second transistor is electrically coupled to a source/drain terminal of the fourth transistor and a gate terminal of the third transistor, and

another source/drain terminal of the first transistor is electrically coupled to a source/drain terminal of the third transistor and a gate terminal of the fourth transistor.

7. The control circuit of claim 6 , further comprising:

a first reset transistor electrically coupled in parallel with the third transistor;

a second reset transistor electrically coupled in parallel with the fourth transistor; and

a reset inverter electrically coupled to gate terminals of each reset transistor.

8. The control circuit of claim 1 , wherein a gate terminal of the first transistor is electrically coupled to ground.

9. A method for controlling dead-time of a direct current to direct current (DC-DC) converter, the method comprising:

providing an output voltage of a DC-DC converter to a first transistor;

determining, via a current sensing circuit, a control current based on a voltage of the first transistor;

providing current to a second transistor electrically coupled to the current sensing circuit, a gate terminal of the second transistor is electrically coupled to a reference voltage;

determining, via a digital up/down counter, a delay count based on the control current;

providing the delay count to a delay cell; and

charging, based on the control current, a capacitor electrically coupled between the current sensing circuit and an input terminal of the digital up/down counter.

10. The method of claim 9 , further comprising closing a switch electrically coupled in parallel with the capacitor based on the control current.

11. The method of claim 9 , wherein the current sensing circuit comprises:

a third transistor and a fourth transistor electrically coupled to each other via a gate terminal and a source/drain terminal of each transistor,

wherein the third transistor is electrically coupled between the second transistor and the fourth transistor via the gate terminal of the third transistor and a source/drain terminal of the second transistor.

12. The method of claim 9 , wherein a gate terminal of the first transistor is electrically coupled to a reference voltage.

13. The method of claim 9 , wherein the current sensing circuit comprises:

a third transistor and a fourth transistor cross coupled between the first transistor and the second transistor,

wherein:

a source/drain terminal of the second transistor is electrically coupled to a source/drain terminal of the fourth transistor and a gate terminal of the third transistor, and

another source/drain terminal of the first transistor is electrically coupled to a source/drain terminal of the third transistor and a gate terminal of the fourth transistor.

14. The method of claim 9 , wherein the current sensing circuit further comprises:

a first reset transistor electrically coupled in parallel with the third transistor;

a second reset transistor electrically coupled in parallel with the fourth transistor; and

a reset inverter electrically coupled to gate terminals of each reset transistor.

15. The method of claim 9 , wherein a gate terminal of the first transistor is electrically coupled to ground.

16. A direct current to direct current (DC-DC) circuit comprising:

one or more delay cells;

a control circuit comprising a current sensing circuit, a transistor, and a digital up/down counter;

the control circuit further comprising an output electrically coupled to an input of the one or more delay cells; and

a high side circuit and a low side circuit coupled to the one or more delay cells and configured to provide an output voltage, the high side circuit and the low side circuit each circuit comprising: a logic gate, one or more inverters, and a transistor;

wherein:

the logic gate, the one or more inverters, and the transistor are electrically coupled together in series;

the transistor is configured to be operational based on a comparison between the output voltage and a gate voltage of the transistor;

the current sensing circuit is configured to either modify or maintain a count of the digital up/down counter; and

the digital up/down counter modifies or maintains a delay time of the one or more delay cells to minimize or eliminate the dead-time of the DC-DC circuit.

17. The control circuit of claim 1 , wherein the second transistor is electrically coupled between the first transistor and the current sensing circuit; and the gate terminal of the second transistor is clamped at approximately zero volts.

18. The method of claim 9 , wherein the second transistor is electrically coupled between the first transistor and the current sensing circuit; and the gate terminal of the second transistor is clamped at approximately zero volts.

19. The DC-DC circuit of claim 16 , further comprising a capacitor electrically coupled between the current sensing circuit and an input terminal of the digital up/down counter.

20. The DC-DC circuit of claim 19 , further comprising a switch electrically coupled in parallel with the capacitor.