Controller, memory system, and operating methods thereof

1. A memory system comprising:

a nonvolatile memory device; and

a controller configured to control the nonvolatile memory device,

wherein the nonvolatile memory device includes a first data storage region in which a memory cell stores one-bit data in a first mode and a second data storage region in which a memory cell stores two-bit or more data in a second mode,

the controller controls the nonvolatile memory device to perform a read operation on the first data storage region and the second data storage region in the second mode,

the controller decodes, as data of the first mode, first data read from the first data storage region through the read operation,

the controller decodes, as data of the second mode, second data read from the second data storage region through the read operation, and

the controller controls the nonvolatile memory device to perform the read operation on the first data storage region in the second mode by changing any one of a plurality of read voltages for reading the data of the second mode to a read voltage value for reading the data of the first mode.

2. The memory system of claim 1 ,

wherein the controller receives and queues a first read command for the first data storage region and a second read command for the second data storage region from a host,

wherein the controller controls the nonvolatile memory device to perform the read operation on the first and second data storage regions in a way interleaving manner based on the queued read commands, and

wherein the controller transmits the decoded first and second data to the host.

3. The memory system of claim 2 , wherein the first and second data storage regions are included in different planes which share a way.

4. The memory system of claim 1 , wherein the controller controls the nonvolatile memory device to perform the read operation the first data storage region only according to a read voltage closest to a read voltage for reading the data of the first mode, among the plurality of read voltages for reading the data of the second mode.

5. The memory system of claim 1 , wherein the first mode is an operation mode in which a plurality of memory cells included in the first data storage region operate as a single-level cell (SLC) and the second mode is an operation mode in which a plurality of memory cells included in the second data storage region operate as at least one of a multi-level cell (MLC), a triple-level cell (TLC), and a quad-level cell (QLC).

6. A controller which controls a nonvolatile memory device, the controller comprising:

a processor configured to control the nonvolatile memory device to perform a read operation, in a second mode, on a first data storage region in which a memory cell stores one-bit data in a first mode, and a second data storage region in which a memory cell stores two-bit or more data in the second mode; and

an error correction code (ECC) engine configured to decode, as data of the first mode, first data read from the first data storage region through the read operation and decode, as data of the second mode, second data read from the second data storage region through the read operation,

wherein the processor controls the nonvolatile memory device to perform the read operation on the first data storage region in the second mode by changing any one of a plurality of read voltages for reading the data of the second mode to a read voltage value for reading the data of the first mode.

7. The controller of claim 6 ,

further comprising a host interface configured to perform data communication with a host,

wherein the processor receives and queues a first read command for the first data storage region and a second read command for the second data storage region, from the host, and

wherein the processor controls the nonvolatile memory device to perform the read operation on the first and second data storage regions in a way interleaving manner based on the queued read commands.

8. The controller of claim 6 , wherein the first and second data storage regions are included in different planes which share a way.

9. The controller of claim 6 , wherein the processor controls the nonvolatile memory device to perform the read operation on the first data storage region only according to a read voltage closest to a read voltage for reading the data of the first mode, among the plurality of read voltages for reading the data of the second mode.

10. The controller of claim 6 , wherein the first mode is an operation mode in which a plurality of memory cells included in the first data storage region operate as a single-level cell (SLC), and the second mode is an operation mode in which a plurality of memory cells included in the second data storage region operate as at least one of a multi-level cell (MLC), a triple-level cell (TLC), and a quad-level cell (QLC).

11. An operating method of a memory system which includes a nonvolatile memory device and a controller configured to control the nonvolatile memory device, the method comprising:

performing, by the nonvolatile memory device, a read operation, in a second mode, on a first data storage region in which a memory cell stores one-bit data in a first mode and a second data storage region in which a memory cell stores two-bit or more data in the second mode; and

decoding, by the controller, first data read from the first data storage region through the read operation, as data of the first mode;

decoding, by the controller, second data read from the second data storage region through the read operation, as data of the second mode,

wherein the read operation is performed on the first data storage region in the second mode by changing any one of a plurality of read voltages for reading the data of the second mode to a read voltage value for reading the data of the first mode.

12. The method of claim 11 , further comprising:

receiving and queuing, by the controller, a first read command for the first data storage region and a second read command for the second data storage region from a host; and

transmitting, by the controller, the decoded first and second data to the host,

wherein the read operation is performed on the first and second data storage regions in a way interleaving manner based on the queued read commands.

13. The method of claim 12 , wherein the first and second data storage regions are included in different planes which share a way.

14. The method of claim 11 , wherein the read operation is performed on the first data storage region only according to a read voltage closest to a read voltage for reading the data of the first mode, among the plurality of read voltages for reading the data of the second mode.

15. The method of claim 11 , wherein the first mode is an operation mode in which a plurality of memory cells included in the first data storage region operate as a single-level cell (SLC), and the second mode is an operation mode in which a plurality of memory cells included in the second data storage region operate as at least one of a multi-level cell (MLC), a triple-level cell (TLC), and a quad-level cell (QLC).

16. An operating method of a controller which controls a nonvolatile memory device, the method comprising:

controlling the nonvolatile memory device to perform a read operation, in a second mode, on a first data storage region in which a memory cell stores one-bit data in a first mode, and a second data storage region in which a memory cell stores two-bit or more data in the second mode;

decoding, as data of the first mode, first data read from the first data storage region through the read operation; and

decoding, as data of the second mode, second data read from the second data storage region through the read operation,

wherein the controlling of the nonvolatile memory device includes controlling the nonvolatile memory device to perform the read operation on the first data storage region in the second mode by changing any one of a plurality of read voltages for reading the data of the second mode to a read voltage value for reading the data of the first mode.

17. The method of claim 16 , further comprising:

receiving and queuing a first read command for the first data storage region and a second read command for the second data storage region from a host; and

transmitting the decoded first and second data to the host,

wherein the controlling of the nonvolatile memory device includes controlling the nonvolatile memory device to perform the read operation on the first and second data storage regions in a way interleaving manner based on the queued read commands.

18. The method of claim 16 , wherein the first and second data storage regions are included in different planes which share a way.

19. The method of claim 16 , wherein the controlling of the nonvolatile memory device includes controlling the nonvolatile memory device to perform the read operation on the first data storage region only according to a read voltage closest to a read voltage for reading the data of the first mode, among the plurality of read voltages for reading the data of the second mode.

20. The method of claim 16 , wherein the first mode is an operation mode in which a plurality of memory cells included in the first data storage region operate as a single-level cell (SLC), and the second mode is an operation mode in which a plurality of memory cells included in the second data storage region operate as at least one of a multi-level cell (MLC), a triple-level cell (TLC), and a quad-level cell (QLC).

21. An operating method of a controller for controlling a memory device including a first storage region having single-level cells and a second storage region having multiple-level cells, the first and second storage regions sharing a way, the method comprising:

controlling the memory device to read out, by using one or more among plural read voltages for the multiple-level cell, first and second data respectively from the first and second regions according to a way-interleaving scheme; and

error-correcting the first data according to an error correction scheme for the single-level cell and the second data according to an error correction scheme for the multiple-level cell,

wherein the controlling includes controlling the memory device to change, to read out the first data during the read out, a selected one of the plural read voltages to a read voltage for the single-level cell, and

wherein the selected read voltage is closest, of the plural read voltages, to the read voltage for the single-level cell.