Shift register, gate drive circuit, driving method thereof, and display device

1. A shift register, comprising: an input sub-circuit, an output sub-circuit, and an output control sub-circuit, wherein:

the input sub-circuit is configured to provide a signal of a first reference voltage signal terminal to a pull-up node under control of an input signal terminal;

the output sub-circuit is configured to provide a signal of a clock signal terminal to a first signal output terminal under control of a potential of the pull-up node; and

the output control sub-circuit is configured to provide a signal of the first signal output terminal to a second signal output terminal under joint control of an output control signal terminal, a third reference voltage signal terminal, and a fourth reference voltage signal terminal;

wherein the output control sub-circuit comprises: a twelfth transistor, a thirteenth transistor and a fourteenth transistor, wherein:

a gate and a first electrode of the twelfth transistor are connected with the fourth reference voltage signal terminal, and a second electrode of the twelfth transistor is connected with a second node;

a gate of the thirteenth transistor is connected with the output control signal terminal, a first electrode of the thirteenth transistor is connected with the third reference voltage signal terminal, and a second electrode of the thirteenth transistor is connected with the second node; and

a gate of the fourteenth transistor is connected with the second node, a first electrode of the fourteenth transistor is connected with the first signal output terminal, and a second electrode of the fourteenth transistor is connected with the second signal output terminal;

wherein the thirteenth transistor has a channel width to length ratio greater than that of the twelfth transistor.

2. The shift register according to claim 1 , wherein the shift register further comprises: a first pull-down node control sub-circuit, a pull-up node control sub-circuit, a second pull-down node control sub-circuit, and a reset sub-circuit, wherein:

the first pull-down node control sub-circuit is configured to provide a signal of the fourth reference voltage signal terminal to a pull-down node under control of the fourth reference voltage signal terminal;

the pull-up node control sub-circuit is configured to provide a signal of the third reference voltage signal terminal to the pull-up node and the first signal output terminal under control of a potential of the pull-down node;

the second pull-down node control sub-circuit is configured to provide the signal of the third reference voltage signal terminal to the pull-down node and a first node respectively, under control of the potential of the pull-up node; and

the reset sub-circuit is configured to provide a signal of a second reference voltage signal terminal to the pull-up node under control of a reset signal terminal.

3. The shift register according to claim 1 , wherein the input sub-circuit comprises a first transistor, wherein:

a gate of the first transistor is connected with the input signal terminal, a first electrode of the first transistor is connected with the first reference voltage signal terminal, and a second electrode of the first transistor is connected with the pull-up node.

4. The shift register according to claim 2 , wherein the first pull-down node control sub-circuit comprises: an eighth transistor and a ninth transistor, wherein:

a gate of the eighth transistor is connected with the first node, a first electrode of the eighth transistor is connected with the fourth reference voltage signal terminal, and a second electrode of the eighth transistor is connected with the pull-down node; and

a gate and a first electrode of the ninth transistor are connected with the fourth reference voltage signal terminal, and a second electrode of the ninth transistor is connected with the first node.

5. The shift register according to claim 2 , wherein the output sub-circuit comprises: a third transistor and a first capacitor, wherein:

a gate of the third transistor is connected with the pull-up node, a first electrode of the third transistor is connected with the clock signal terminal, and a second electrode of the third transistor is connected with the first signal output terminal; and

one terminal of the first capacitor is connected with the pull-up node, and the other terminal of the first capacitor is connected with the first signal output terminal.

6. The shift register according to claim 2 , wherein the pull-up node control sub-circuit comprises: a tenth transistor and a fourth transistor, wherein:

a gate of the tenth transistor is connected with the pull-down node, a first electrode of the tenth transistor is connected with the third reference voltage signal terminal, and a second electrode of the tenth transistor is connected with the pull-up node; and

a gate of the fourth transistor is connected with the pull-down node, a first electrode of the fourth transistor is connected with the third reference voltage signal terminal, and a second electrode of the fourth transistor is connected with the first signal output terminal.

7. The shift register according to claim 2 , wherein the second pull-down node control sub-circuit comprises: a sixth transistor and a seventh transistor, wherein:

a gate of the sixth transistor is connected with the pull-up node, a first electrode of the sixth transistor is connected with the third reference voltage signal terminal, and a second electrode of the sixth transistor is connected with the pull-down node; and

a gate of the seventh transistor is connected with the pull-up node, a first electrode of the seventh transistor is connected with third reference voltage signal terminal, and a second electrode of the seventh transistor is connected with the first node.

8. The shift register according to claim 2 , wherein the reset sub-circuit comprises a second transistor, wherein:

a gate of the second transistor is connected with the reset signal terminal, a first electrode of the second transistor is connected with the second reference voltage signal terminal, and a second electrode of the second transistor is connected with the pull-up node.

9. The shift register according to claim 1 , wherein the shift register further comprises: a first denoising sub-circuit and/or a second denoising sub-circuit, wherein:

the first denoising sub-circuit is configured to provide a signal of the third reference voltage signal terminal to the pull-up node under control of a first denoising control terminal; and

the second denoising sub-circuit is configured to provide the signal of the third reference voltage signal terminal to the first signal output terminal under control of a second denoising control terminal.

10. The shift register according to claim 9 , wherein the first denoising sub-circuit comprises an eleventh transistor, wherein:

a gate of the eleventh transistor is connected with the first denoising control terminal, a first electrode of the eleventh transistor is connected with the third reference voltage signal terminal, and a second electrode of the eleventh transistor is connected with the pull-up node.

11. The shift register according to claim 9 , wherein the second denoising sub-circuit comprises a fifth transistor, wherein:

a gate of the fifth transistor is connected with the second denoising control terminal, a first electrode of the fifth transistor is connected with the third reference voltage signal terminal, and a second electrode of the fifth transistor is connected with the first signal output terminal.

12. The shift register according to claim 3 , wherein each transistor is an N-type transistor or a P-type transistor.

13. A gate drive circuit, comprising a plurality of cascaded shift registers according to claim 1 , wherein:

a first signal output terminal of a shift register at each other level than a first level of the plurality of cascaded shift registers is connected with a reset signal terminal of a shift register at a preceding level adjacent thereto;

a first signal output terminal of a shift register at each other level than a last level of the plurality of cascaded shift registers is connected with an input signal terminal of a shift register at a succeeding level adjacent thereto; and

second signal output terminals of shift registers at respective levels are configured to provide driving signals to corresponding gate lines of a display panel.

14. The gate drive circuit according to claim 13 , wherein each of the plurality of cascaded shift registers further comprises: a first pull-down node control sub-circuit, a pull-up node control sub-circuit, a second pull-down node control sub-circuit, and a reset sub-circuit, wherein:

the first pull-down node control sub-circuit is configured to provide a signal of a fourth reference voltage signal terminal to a pull-down node under control of the fourth reference voltage signal terminal;

the pull-up node control sub-circuit is configured to provide a signal of a third reference voltage signal terminal to a pull-up node and a first signal output terminal under control of a potential of the pull-down node;

the second pull-down node control sub-circuit is configured to provide the signal of the third reference voltage signal terminal to the pull-down node and a first node respectively under control of a potential of the pull-up node; and

the reset sub-circuit is configured to provide a signal of a second reference voltage signal terminal to the pull-up node under control of a reset signal terminal.

15. The gate drive circuit according to claim 13 , wherein each of the plurality of cascaded shift registers further comprises: a first denoising sub-circuit and/or a second denoising sub-circuit, wherein:

the first denoising sub-circuit is configured to provide a signal of a third reference voltage signal terminal to a pull-up node under control of a first denoising control terminal; and

the second denoising sub-circuit is configured to provide the signal of the third reference voltage signal terminal to a first signal output terminal under control of a second denoising control terminal.

16. The gate drive circuit according to claim 13 , an input signal terminal of a shift register at the first level is connected with a frame start signal terminal, and a reset signal terminal of a shift register at the last level is connected with a frame end signal terminal.

17. The gate drive circuit according to claim 13 , clock signals to clock signal terminals of two adjacent shift registers are clock signals with opposite phases and a same period.

18. A method for driving the gate drive circuit according to claim 13 , the method comprising:

outputting, by a first signal output terminal of a shift register, a cascading signal to a shift register at a next level;

providing, by an output control signal terminal of the shift register, a first electric level to an output control sub-circuit of the shift register so that a second signal output terminal of the shift register outputs a gate driving signal to a corresponding gate line; and

providing, by the output control signal terminal of the shift register, a second electric level to the output control sub-circuit of the shift register so that the second signal output terminal of the shift register stops outputting the gate driving signal to the corresponding gate line.

19. A display device, comprising the gate drive circuit according to claim 13 .