Middle of the line contact formation

1. A method of forming a semiconductor device comprising:

forming a semiconductor structure comprising a semiconductor substrate having two or more fins, a plurality of recessed gate structures disposed on at least a portion of each of the fins, a gate cap layer disposed on a top surface of the recessed gate structures, gate spacers disposed on sidewalls of the recessed gate structures and the gate cap layer, a source/drain region in a recessed region of the semiconductor substrate between each adjacent gate spacer, a first conductive material disposed on a top surface of each of the source/drain regions, and a first optical planarization layer disposed over a top surface of the semiconductor structure;

etching the first optical planarization layer on one of the fins and exposing a top surface of each of the gate spacers, the gate cap layer and a portion of the first conductive material adjacent to the exposed gate spacers to form a first gate contact opening;

depositing a sacrificial place-holder material in the first gate contact opening;

removing the first optical planarization layer; and

recessing the first conductive material.

2. The method of claim 1 , further comprising:

selectively growing a metal layer on the recessed first conductive material to below a top surface of the gate spacers; and

depositing a dielectric layer on a top surface of the metal layer, gate spacers and gate cap layer, wherein the dielectric layer is coplanar with the sacrificial place-holder material.

3. The method of claim 2 , further comprising:

removing the sacrificial place-holder material to form an opening; and

depositing a second optical planarization layer in the opening.

4. The method of claim 3 , further comprising:

removing the second optical planarization layer to form a second gate contact opening; and

depositing a second conductive material in the second gate contact opening.

5. The method of claim 1 , wherein the gate cap layer and the sacrificial place-holder material are the same and comprise SiC or SiCO.

6. The method of claim 2 , wherein the metal layer and the first conductive material are different metals.

7. The method of claim 6 , wherein the metal layer comprises tungsten and the first conductive material comprises cobalt.

8. The method of claim 4 , wherein the first conductive material and the second conductive material are the same or different and comprise a metal selected from the group consisting of copper, cobalt, aluminum, lead and tungsten.

9. A method of forming a semiconductor device comprising:

forming a semiconductor structure comprising a semiconductor substrate having two or more fins, a plurality of recessed gate structures disposed on at least a portion of each of the fins, a gate cap layer disposed on a top surface of the recessed gate structures, gate spacers disposed on sidewalls of each of the recessed gate structures and the gate cap layer, a source/drain region in a recessed region of the semiconductor substrate between each adjacent gate spacer, a first conductive material disposed on a top surface of each of the source/drain regions, and a first optical planarization layer over a top surface of the semiconductor structure;

etching the first optical planarization layer on one of the fins and exposing a top surface of each of the gate spacers, the gate cap layer and a portion of the first conductive material adjacent to the exposed gate spacers to form a first gate contact opening;

depositing a liner layer in the first gate contact opening;

depositing a sacrificial place-holder material on the liner layer and filling the first gate contact opening;

removing the first optical planarization layer; and

recessing the first conductive material.

10. The method of claim 9 , further comprising:

selectively growing a metal layer on the recessed first conductive material to below a top surface of the gate spacers; and

depositing a dielectric layer on a top surface of the metal layer, gate spacers and gate cap layer, wherein the dielectric layer is coplanar with the liner layer and the sacrificial place-holder material.

11. The method of claim 10 , further comprising:

removing the sacrificial place-holder material to form an opening;

removing the liner layer from a bottom surface of the opening exposing recessed the gate structures and the gate spacers;

removing a portion of the gate spacers to below a top surface of the recessed gate structures; and

depositing a second conductive material in the opening to form a gate contact.

12. The method of claim 11 , wherein the portion of the gate spacers is removed by atomic layer etching.

13. The method of claim 11 , wherein about 10 nanometers of the gate spacers is removed.

14. The method of claim 9 , wherein the liner layer comprises SiO 2 and the sacrificial place-holder material comprises SiN.

15. The method of claim 10 , wherein the metal layer and the first conductive material are different metals.

16. The method of claim 15 , wherein the metal layer comprises tungsten and the first conductive material comprises cobalt.

17. The method of claim 11 , wherein the first conductive material and the second conductive material are the same or different and comprise a metal selected from the group consisting of copper, cobalt, aluminum, lead and tungsten.

18. The method of claim 10 , wherein the first gate contact opening is not aligned with the recessed gate structures.

19. A method comprising:

forming a semiconductor structure comprising a semiconductor substrate having two or more fins, a plurality of recessed gate structures disposed on at least a portion of each of the fins, a gate cap layer disposed on a top surface of each of the gate structures, gate spacers disposed on sidewalls of each of the gate structures and the gate cap layers, a source/drain region in a recessed region of the semiconductor substrate between each adjacent gate spacer, a first interlevel dielectric layer disposed on a top surface of each of the source/drain regions, and a first optical planarization layer disposed over a top surface of the semiconductor structure;

selectively etching the first optical planarization layer on one of the fins and removing the first interlevel dielectric layer and a portion of each of the gate spacers to form a first opening, wherein an upper portion of the gate spacers has a tapered shape;

removing the first optical planarization layer;

depositing a first conductive material in the first opening; recessing the first conductive material to a bottom portion of the tapered shape of the gate spacer to form a second opening;

depositing a cap layer in the second opening;

depositing a second optical planarization layer on the top surface of the semiconductor structure;

forming an opening in the second optical planarization layer exposing at least a top surface of the cap layer;

depositing a sacrificial place-holder material in the opening;

removing the second optical planarization layer; and

recessing the gate structures.

20. The method of claim 19 , further comprising:

depositing a liner layer on the recessed gate structures;

depositing a second interlevel dielectric layer on the liner layer;

depositing a third optical planarization layer on the second interlevel dielectric layer;

selectively removing a portion of the liner layer, second interlevel dielectric layer and third optical planarization layer to form a trench exposing a top surface of the recessed gate structures; and

depositing a second conductive material in the trench.