Solid-state image capture element and electronic device enabled to eliminate asymmetry of a light reception amount
The present disclosure relates to a solid-state image capture element and an electronic device which are enabled to eliminate asymmetry of a light reception amount in accordance with an incident angle of light incident on a pixel. A solid-state image capture element includes: a pixel including a light-receiving portion that receives light incident from a rear-surface side of a semiconductor substrate; and a wiring layer laminated on a front-surface of the semiconductor substrate. The pixel includes a symmetrical wiring that is formed symmetrically with respect to a center of the pixel in a plane view of the pixel. The symmetrical wiring is arranged in a layer closest to the light-receiving portion, of a plurality of layers of wiring formed in the wiring layer. For example, the present technology can be applied to a rear-surface irradiation type solid-state image capture element.
1. A solid-state image capture element, comprising:
first and second pixels each including a light-receiving portion that receives light incident from a rear-surface side of a semiconductor substrate; and
a wiring layer laminated on a front-surface of the semiconductor substrate,
wherein the first pixel is adjacent to the second pixel,
wherein the first pixel includes a single symmetrical wiring that is formed symmetrically with respect to a center of the first pixel in a plane view of the first pixel in a layer closest to the light-receiving portion of a plurality of layers of wirings in the wiring layer,
wherein the second pixel includes a single asymmetrical wiring that is formed asymmetrically with respect to a center of the second pixel in a plane view of the second pixel in the layer closest to the light-receiving portion of the plurality of layers of wirings in the wiring layer in a non-overlapping manner with wirings in layers of the plurality of layers of wirings beneath the layer closest to the light-receiving portion in a cross-sectional view, and
wherein the single symmetrical wiring overlaps wirings in layers of the plurality of layers of wirings provided beneath the single symmetrical wiring except for a wiring in one of the layers of the plurality of layers of wirings provided closest to the single asymmetrical wiring.
2. The solid-state image capture element according to claim 1 , wherein a gap of a predetermined distance is provided between the second pixel and the single symmetrical wiring.
3. The solid-state image capture element according to claim 2 , wherein the single asymmetrical wiring has a predetermined width from a boundary of the first pixel.
4. The solid-state image capture element according to claim 2 ,
wherein in the first pixel, the predetermined distance provided between the second pixel and the single symmetrical wiring is corrected in accordance with an arrangement position of the first pixel.
5. The solid-state image capture element according to claim 3 , wherein the predetermined width of the single asymmetrical wiring is corrected in accordance with an arrangement position of the second pixel.
6. The solid-state image capture element according to claim 1 , wherein the first pixel is a pixel configured to receive red light, and the second pixel is a pixel configured to receive green light.
7. The solid-state image capture element according to claim 1 , wherein the first pixel is a pixel configured to receive light having a wavelength of 620 nm or more.
8. The solid-state image capture element according to claim 1 , wherein the single asymmetrical wiring shields light reflected from wirings in layers beneath the layer closest to the light-receiving portion of the plurality of layers of wirings in the wiring layer of the first pixel.
9. The solid-state image capture element according to claim 8 , wherein the single asymmetrical wiring prevents the reflected light from entering the light-receiving portion of the second pixel from a side opposite the rear-surface side of the semiconductor substrate.
10. The solid-state image capture element according to claim 1 , wherein the single symmetrical wiring has a circular or octagonal shape.
11. An electronic device, comprising:
a solid-state image capture element including:
first and second pixels each including a light-receiving portion that receives light incident from a rear-surface side of a semiconductor substrate; and
a wiring layer laminated on a front-surface of the semiconductor substrate,
wherein the first pixel is adjacent to the second pixel,
wherein the first pixel includes a single symmetrical wiring that is formed symmetrically with respect to a center of the first pixel in a plane view of the first pixel in a layer closest to the light-receiving portion of a plurality of layers of wirings in the wiring layer,
wherein the second pixel includes a single asymmetrical wiring that is formed asymmetrically with respect to a center of the second pixel in a plane view of the second pixel in the layer closest to the light-receiving portion of the plurality of layers of wirings in the wiring layer in a non-overlapping manner with wirings in layers of the plurality of layers of wirings beneath the layer closest to the light-receiving portion in a cross-sectional view, and
wherein the single symmetrical wiring overlaps wirings in layers of the plurality of layers of wirings provided beneath the single symmetrical wiring except for a wiring in one of the layers of the plurality of layers of wirings provided closest to the single asymmetrical wiring.
12. The electronic device according to claim 11 , wherein a gap of a predetermined distance is provided between the second pixel and the single symmetrical wiring.
13. The electronic device according to claim 12 , wherein the single asymmetrical wiring has a predetermined width from a boundary of the first pixel.
14. The electronic device according to claim 12 , wherein in the first pixel, the predetermined distance provided between the second pixel and the single symmetrical wiring is corrected in accordance with an arrangement position of the first pixel.
15. The electronic device according to claim 13 , wherein the predetermined width of the single asymmetrical wiring is corrected in accordance with an arrangement position of the second pixel.
16. The electronic device according to claim 11 , wherein the first pixel is a pixel configured to receive red light, and the second pixel is a pixel configured to receive green light.
17. The electronic device according to claim 11 , wherein the first pixel is a pixel configured to receive light having a wavelength of 620 nm or more.
18. The electronic device according to claim 11 , wherein the single asymmetrical wiring shields light reflected from wirings in layers beneath the layer closest to the light-receiving portion of the plurality of layers of wirings in the wiring layer of the first pixel.
19. The electronic device according to claim 18 , wherein the single asymmetrical wiring prevents the reflected light from entering the light-receiving portion of the second pixel from a side opposite the rear-surface side of the semiconductor substrate.
20. The electronic device according to claim 11 , wherein the single symmetrical wiring has a circular or octagonal shape.