Transistor including electride electrode
Provided are transistors including an electride electrode. The transistor includes a substrate, a source region and a drain region doped with ions of different polarity from the substrate in a surface of the substrate, a source electrode and a drain electrode including an electride material on the source region and the drain region, a gate insulating layer surrounding the source electrode and a drain electrode on the substrate, and a gate electrode between the source electrode and the drain electrode on the substrate. The source electrode and the drain electrode have an ohmic contact with the substrate.
1. A transistor comprising:
a doped substrate;
a source region and a drain region doped with ions of a polarity different from that of the doped substrate in a surface of the doped substrate;
a source electrode and a drain electrode comprising an electride material on the source region and drain region, respectively;
a gate insulating layer on the doped substrate to surround the source electrode and the drain electrode; and
a gate electrode on the doped substrate between the source electrode and the drain electrode,
wherein each of the source electrode and the drain electrode is a single layer.
2. The transistor of claim 1 , further comprising a metal layer on the gate insulating layer to cover the source electrode and the drain electrode.
3. The transistor of claim 1 , wherein the source electrode and the drain electrode contact the source region and the drain region, respectively, and the source electrode and the drain electrode comprise an YsSi 3 electride.
4. The transistor of claim 1 , further comprising a passivation layer on lower sides of the source electrode and the drain electrode to contact the substrate.
5. The transistor of claim 4 , wherein the source electrode and the drain electrode comprise a C 12 A 7 electride or a YsSi 3 electride.
6. The transistor of claim 4 , wherein the source electrode and the drain electrode comprise a two-dimensional (2D) electride and the 2D electride is Ca 2 N, Y 2 C, and Gd 2 C or a combination or subcombination thereof.
7. The transistor of claim 6 , wherein the 2D electride is a single crystal including an interlayer electron layer, and the interlayer electron layer of the 2D electride is vertically arranged with respect to the surface of the doped substrate.
8. The transistor of claim 4 , wherein the passivation layer comprises a Group VI material layer configured to combine with a dangling bond on a surface of the doped substrate.
9. The transistor of claim 8 , wherein the Group VI material layer comprises Se or S.
10. The transistor of claim 8 , wherein the passivation layer has a thickness that is less than that of the gate insulating layer.
11. The transistor of claim 8 , wherein the Group VI material layer has a thickness of one layer to about five layers thereof.
12. The transistor of claim 4 , wherein the passivation layer is an insulating layer.
13. The transistor of claim 1 , further comprising an insulating layer on the doped substrate to cover the source region and the drain region, wherein the source electrode and the drain electrode and the gate insulating layer are on the insulating layer.
14. The transistor of claim 13 , wherein the insulating layer has a thickness less than that of the gate insulating layer.
15. The transistor of claim 14 , wherein the insulating layer comprises silicon oxide or silicon nitride.
16. The transistor of claim 15 , wherein the insulating layer comprises one layer to about five layers thereof.
17. A transistor comprising:
a doped substrate;
a source region and a drain region doped with ions of a polarity different from that of the doped substrate in a surface of the doped substrate;
a source electrode and a drain electrode comprising an electride material on the source region and drain region, respectively;
a gate insulating layer on the doped substrate to surround the source electrode and the drain electrode;
a gate electrode on the doped substrate between the source electrode and the drain electrode;
a passivation layer on lower sides of the source electrode and the drain electrode to contact the substrate, the passivation layer comprising a Group VI material layer configured to combine with a dangling bond on a surface of the doped substrate; and
a single graphene layer between the Group VI material layer and the source electrode and the drain electrode.
18. A transistor comprising:
a doped substrate;
a source region and a drain region doped with ions of a polarity different from that of the doped substrate in a surface of the doped substrate;
a source electrode and a drain electrode comprising an electride material on the source region and drain region, respectively;
a gate insulating layer on the doped substrate to surround the source electrode and the drain electrode;
a gate electrode on the doped substrate between the source electrode and the drain electrode;
a passivation layer on lower sides of the source electrode and the drain electrode to contact the substrate; and
a single graphene layer between the insulating layer and the source electrode and the drain electrode,
wherein the passivation layer is an insulating layer.