Dynamic precision for neural network compute operations
In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.
1. A graphics multiprocessor comprising:
an instruction cache to receive a stream of instructions;
an instruction unit to dispatch instructions in the stream of instructions for execution;
a compute engine comprising a fused component block comprising a high precision single instruction, multiple data (SIMD) processor which operates at a high speed and a low precision floating point single instruction, multiple data (SIMD) processor which operates at a low speed;
a shared cache memory communicatively coupled to the high-precision component and low-precision component; and
a processor to:
receive instructions from the instruction unit for execution in the compute engine;
select, based at least in part on a compute requirement of the instructions, at least one of the high precision SIMD processor or the low precision SIMD processor to execute the instructions; and
apply a gate to at least one of the high precision SIMD processor or the low precision SIMD processor to execute the instructions.
2. The graphics multiprocessor of claim 1 , wherein:
the gate comprises a clock gate.
3. The graphics multiprocessor of claim 1 , wherein:
the gate comprises a power gate.
4. A computer-based method, comprising:
receiving instructions from an instruction unit for execution in a compute engine, the compute engine comprising a fused component block comprising a high precision single instruction, multiple data (SIMD) processor which operates at a high speed and a low precision floating point single instruction, multiple data (SIMD) processor which operates at a low speed;
selecting, based at least in part on a compute requirement of the instructions, at least one of the high precision SIMD processor or the low precision SIMD processor to execute the instructions; and
applying a gate to at least one of the high precision SIMD processor or the low precision SIMD processor to execute the instructions.
5. The method of claim 4 , wherein:
the gate comprises a clock gate.
6. The method of claim 4 , wherein:
the gate comprises a power gate.
7. A non-transitory computer-readable medium comprising instructions which, when executed by a processor, cause the processor to:
receive instructions from an instruction unit for execution in a compute engine, the compute engine comprising a fused component block comprising a high precision single instruction, multiple data (SIMD) processor which operates at a high speed and a low precision floating point single instruction, multiple data (SIMD) processor which operates at a low speed;
select, based at least in part on a compute requirement of the instructions, at least one of the high precision SIMD processor or the low precision SIMD processor to execute the instructions; and
apply a gate to at least one of the high precision SIMD processor or the low precision SIMD processor to execute the instructions.
8. The computer-readable medium of claim 7 , wherein:
the gate comprises a clock gate.
9. The computer-readable medium of claim 7 , wherein:
the gate comprises a power gate.