Shift register, semiconductor device, display device, and electronic device
The invention provides a semiconductor device and a shift register, in which low noise is caused in a non-selection period and a transistor is not always on. First to fourth transistors are provided. One of a source and a drain of the first transistor is connected to a first wire, the other of the source and the drain thereof is connected to a gate electrode of the second transistor, and a gate electrode thereof is connected to a fifth wire. One of a source and a drain of the second transistor is connected to a third wire and the other of the source and the drain thereof is connected to a sixth wire. One of a source and a drain of the third transistor is connected to a second wire, the other of the source and the drain thereof is connected to the gate electrode of the second transistor, and a gate electrode thereof is connected to a fourth wire. One of a source and a drain of the fourth transistor is connected to the second wire, the other of the source and the drain thereof is connected to the sixth wire, and a gate electrode thereof is connected to the fourth wire.
1. A semiconductor device comprising:
a stage comprising:
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor; and
a capacitor,
wherein one of a source and a drain of the first transistor, one of a source and a drain of the second transistor, one of a source and a drain of the fifth transistor, a first electrode of the capacitor, and an output terminal of the stage are electrically connected to one another,
wherein a gate of the first transistor, one of a source and a drain of the third transistor, one of a source and a drain of the fourth transistor, and a second electrode of the capacitor are electrically connected to one another,
wherein a gate of the fourth transistor, the other of the source and the drain of the fourth transistor, and an output terminal of a preceding stage are electrically connected to one another,
wherein a gate of the second transistor and a gate of the third transistor are electrically connected to one another,
wherein a gate signal line is electrically connected to the output terminal of the stage,
wherein a power source line is electrically connected to the other of the source and the drain of the second transistor, the other of the source and the drain of the third transistor, and the other of the source and the drain of the fifth transistor,
wherein a first clock signal line is electrically connected to the other of the source and the drain of the first transistor,
wherein a second clock signal line is electrically connected to a gate of the fifth transistor, and
wherein the power source line is located between the first to second clock signal lines and the output terminal of the stage, and each of the first to second clock signal lines is not located between the power source line and the output terminal of the stage.
2. A semiconductor device comprising:
a stage comprising:
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor; and
a capacitor,
wherein one of a source and a drain of the first transistor, one of a source and a drain of the second transistor, one of a source and a drain of the fifth transistor, a first electrode of the capacitor, and an output terminal of the stage are electrically connected to one another,
wherein a gate of the first transistor, one of a source and a drain of the third transistor, one of a source and a drain of the fourth transistor, and a second electrode of the capacitor are electrically connected to one another,
wherein a gate of the fourth transistor, the other of the source and the drain of the fourth transistor, and an output terminal of a preceding stage are electrically connected to one another,
wherein a gate of the second transistor and a gate of the third transistor are electrically connected to one another,
wherein a conductive layer comprises the gate of the second transistor and the gate of the third transistor,
wherein a gate signal line is electrically connected to the output terminal of the stage,
wherein a power source line is electrically connected to the other of the source and the drain of the second transistor, the other of the source and the drain of the third transistor, and the other of the source and the drain of the fifth transistor,
wherein a first clock signal line is electrically connected to the other of the source and the drain of the first transistor,
wherein a second clock signal line is electrically connected to a gate of the fifth transistor, and
wherein the power source line is located between the first to second clock signal lines and the output terminal of the stage, and each of the first to second clock signal lines is not located between the power source line and the output terminal of the stage.