Semiconductor device with nanowire capacitor plugs and method for fabricating the same

1. A semiconductor device, comprising:

a substrate including a plurality of first regions and second regions;

a plurality of capacitor contacts positioned respectively over the plurality of second regions, at least one of the plurality of capacitor contacts having a neck portion and a head portion over the neck portion, wherein an upper width of the head portion is larger than an upper width of the neck portion;

a plurality of bit line contacts positioned respectively over the plurality of first regions and a plurality of bit lines positioned respectively over the plurality of bit line contacts, wherein at least one of the plurality of bit line is a wavy line extending between two adjacent capacitor contacts;

a plurality of capacitor plugs disposed respectively over the plurality of capacitor contacts, wherein the plurality of capacitor plugs comprises a plurality of nanowires, a conductive liner disposed over the plurality of nanowires, and a conductor disposed over the conductive liner; and

a plurality of capacitor structures disposed respectively over the plurality of capacitor plugs.

2. The semiconductor device of claim 1 , further comprising a plurality of landing pads disposed respectively over the plurality of head portions, at least one of the plurality of landing pads comprising a protruding portion of the capacitor plug and a first spacer over the protruding portion, wherein a width of the first spacer is larger than a width of the capacitor plug.

3. The semiconductor device of claim 2 , wherein the first spacer comprises metal silicide and is disposed on a sidewall of the protruding portion.

4. The semiconductor device of claim 2 , wherein the first spacer comprises polysilicon and is disposed on a sidewall of the protruding portion.

5. The semiconductor device of claim 4 , further comprising a second spacer disposed over the first spacer.

6. The semiconductor device of claim 5 , wherein the second spacer comprises metal silicide.

7. The semiconductor device of claim 1 , wherein the upper width of the head portion is larger than a bottom width of the head portion.

8. The semiconductor device of claim 1 , wherein the upper width of the neck portion is substantially the same as a bottom width of the head portion.

9. The semiconductor device of claim 1 , wherein the head portion has a curved sidewall.

10. The semiconductor device of claim 1 , wherein the head portion has tapered profile.

11. A method for fabricating a semiconductor device, comprising:

providing a substrate including a plurality of first regions and second regions;

forming a plurality of bit line contacts respectively over the first regions of the substrate;

forming a plurality of capacitor contacts respectively over the second regions of the substrate, wherein at least one of the plurality of capacitor contacts having a neck portion and a head portion over the neck portion, wherein an upper width of the head portion is larger than an upper width of the neck portion;

forming a plurality of bit lines respectively over the plurality of bit line contacts, wherein at least one of the plurality of bit line is a wavy line extending between two adjacent capacitor contacts;

forming a plurality of capacitor plugs respectively over the plurality of capacitor contacts, wherein the plurality of capacitor plugs comprises a plurality of nanowires, a conductive liner disposed over the nanowires, and a conductor disposed over the conductive liner; and

forming a plurality of capacitor structures respectively over the plurality of capacitor plugs.

12. The method for fabricating a semiconductor device of claim 11 , further comprising: forming a plurality of landing pads disposed respectively over the plurality of head portions, at least one of the plurality of landing pads comprising a protruding portion of the capacitor plug and a first spacer over the protruding portion, wherein a width of the first spacer is larger than a width of the capacitor plug.

13. The method for fabricating a semiconductor device of claim 12 , wherein the first spacer comprises metal silicide and is formed on a sidewall of the protruding portion.

14. The method for fabricating a semiconductor device of claim 12 , wherein the first spacer comprises polysilicon and is disposed on a sidewall of the protruding portion.

15. The method for fabricating a semiconductor device of claim 14 , further comprising: forming a plurality of second spacers respectively over the plurality of first spacers.

16. The method for fabricating a semiconductor device of claim 15 , wherein the second spacer comprises metal silicide.

17. The method for fabricating the semiconductor device of claim 11 , wherein forming a plurality of capacitor contacts comprise:

forming a contact hole in a dielectric stack having a first layer and a second layer over the first layer;

removing a portion of the second layer around the contact hole to form a transformed hole having a narrow portion in the first layer and a wide portion in the second layer; and

filling a conductive material into the transformed hole.

18. The method for fabricating the semiconductor device of claim 17 , wherein the contact hole is formed integrally with a bit line trench in the second layer.

19. The method for fabricating the semiconductor device of claim 18 , further comprising:

filling the bit line trench and a lower portion of the contact hole with a filling material.

20. The method for fabricating the semiconductor device of claim 19 , wherein removing a portion of the second layer around the contact hole is performed after filling the lower portion of the contact hole with a sacrificial material.