Closely packed vertical transistors with reduced contact resistance
A method of forming a semiconductor device and resulting structures having closely packed vertical transistors with reduced contact resistance by forming a semiconductor structure on a doped region of a substrate, the semiconductor structure including a gate formed over a channel region of a semiconductor fin. A liner is formed on the gate and the semiconductor fin, and a dielectric layer is formed on the liner. Portions of the liner are removed to expose a top surface and sidewalls of the semiconductor fin and a sidewall of the dielectric layer. A recessed opening is formed by recessing portions of the liner from the exposed sidewall of the dielectric layer. A top epitaxy region is formed on the exposed portions of the semiconductor fin and dielectric layer such that an extension of the top epitaxy region fills the recessed opening. The top epitaxy region is confined between portions of the liner.
1. A method for fabricating a semiconductor device, the method comprising:
forming a vertical semiconductor structure on a bottom doped region of a substrate, the vertical semiconductor structure comprising a gate formed over a channel region of a semiconductor fin, the gate between a bottom spacer and a top spacer;
forming a conformal liner on a surface of the bottom spacer, on a sidewall of the gate, and on a top surface of the top spacer;
removing portions of the conformal liner to expose a top surface and sidewalls of the semiconductor fin;
forming a top epitaxy region on the exposed top surface of the semiconductor fin and the top surface of the top spacer, the top epitaxy region confined between portions of the liner;
forming a first contact on a surface of the bottom doped region, the first contact prevented from electrically shorting to the gate by portions of the liner formed between the first contact and the semiconductor structure; and
forming a second contact wrapping around a top surface and a sidewall of the top epitaxy region, said second contact prevented from electrically shorting to the gate by portions of the liner formed between the second contact and the semiconductor structure.
2. The method of claim 1 , wherein the semiconductor fin is recessed to a surface of the top spacer.
3. The method of claim 1 , wherein the semiconductor fin is recessed below a surface of the top spacer.
4. The method of claim 1 , wherein the vertical semiconductor structure comprises a plurality of gates, each gate formed over a channel region of a semiconductor fin.
5. The method of claim 4 , further comprising a plurality of top epitaxy regions, each top epitaxy region formed on a surface of a semiconductor fin.
6. The method of claim 5 , wherein portions of the liner prevent a short between adjacent top epitaxy regions.
7. The method of claim 1 , wherein the liner has a thickness of about 3 nm to about 20 nm.
8. The method of claim 1 , wherein the liner has a thickness of about 3 nm to about 8 nm.
9. The method of claim 1 , wherein the liner comprises a nitride liner having a thickness of about 5 nm.
10. The method of claim 1 , wherein a plurality of the semiconductor devices form a plurality of transistors.
11. The method of claim 10 , wherein the plurality of transistors have a fin pitch of about 20 nm to about 100 nm.
12. The method of claim 1 , wherein the first contact is comprised of copper and the second contact is comprised of copper.
13. A method for fabricating a semiconductor device, the method comprising:
forming a semiconductor fin on a substrate;
forming a gate over a channel region of the semiconductor fin, the gate between a bottom spacer and a top spacer;
forming a liner over the semiconductor fin and the gate, the liner positioned on a surface of the bottom spacer, on a sidewall of the gate, and on a top surface of the top spacer;
removing portions of the liner to expose a top surface and sidewalls of the semiconductor fin;
forming a top epitaxy region on the exposed top surface of the semiconductor fin and the top surface of the top spacer, the top epitaxy region confined between sidewalls of the liner;
forming a bottom source/drain contact, wherein the bottom source/drain contact is prevented from electrically shorting to the gate by a first portion of the liner; and
forming a top source/drain contact, wherein the top source/drain contact is prevented from electrically shorting to the gate by a second portion of the liner.
14. The method of claim 13 , wherein the top source/drain contact wraps around a top surface and a sidewall of the top epitaxy region.
15. The method of claim 13 , wherein portions of the liner are recessed in a direction orthogonal to the channel region.
16. The method of claim 13 , wherein the liner comprises a nitride liner having a thickness of about 3 nm to about 20 nm.
17. The method of claim 13 , wherein a plurality of the semiconductor devices comprise a plurality of transistors.
18. The method of claim 17 , wherein the plurality of transistors have a fin pitch of about 20 nm to about 100 nm.
19. The method of claim 17 , wherein the plurality of transistors have a fin pitch of about 30 nm to about 50 nm.
20. The method of claim 13 , wherein the bottom source/drain is comprised of copper and the top source/drain contact is comprised of copper.