Fin field-effect transistor with reduced parasitic capacitance and reduced variability

1. A method for manufacturing a semiconductor device, comprising:

patterning a plurality of semiconductor fins on a semiconductor substrate;

replacing at least two of the plurality of semiconductor fins with a plurality of dummy fins comprising a dielectric material;

forming a gate structure on and around the plurality of semiconductor fins and the plurality of dummy fins; and

forming a source/drain contact adjacent the gate structure;

wherein the patterning of the plurality of semiconductor fins comprises:

forming a plurality of first hardmask portions on the semiconductor substrate, wherein the plurality of first hardmask portions comprise a first material;

replacing at least two of the plurality of first hardmask portions with a plurality of second hardmask portions, wherein the plurality of second hardmask portions comprise a second material different from the first material; and

transferring a pattern of the plurality of first and second hardmask portions to the semiconductor substrate to pattern the plurality of semiconductor fins.

2. The method according to claim 1 , wherein the plurality of semiconductor fins are formed in at least one active region, and the plurality of dummy fins are formed in at least one isolation region.

3. The method according to claim 1 , wherein the plurality of dummy fins are formed between two semiconductor fins of the plurality of semiconductor fins.

4. The method according to claim 1 , wherein the replacing of the at least two of the plurality of semiconductor fins with the plurality of dummy fins comprises:

forming a dielectric fill layer on the semiconductor substrate and between the plurality of semiconductor fins;

selectively removing the plurality of second hardmask portions to expose underlying semiconductor fins of the plurality of semiconductor fins;

removing the exposed underlying semiconductor fins to create a plurality of openings in the dielectric fill layer; and

depositing a dielectric material in the plurality of openings in place of the removed semiconductor fins to form the plurality of dummy fins.

5. The method according to claim 1 , wherein the second material has an etch selectivity with respect to the first material.

6. The method according to claim 1 , wherein forming the gate structure comprises:

forming a dummy gate on and around the plurality of semiconductor fins and the plurality of dummy fins; and

removing the dummy gate and replacing the dummy gate with the gate structure, wherein the gate structure comprises at least one conductive material.

7. The method according to claim 1 , wherein the source/drain contact extends over the plurality of semiconductor fins and the plurality of dummy fins.

8. The method according to claim 1 , wherein the gate structure and source/drain contact are shared between two active transistor regions.

9. A method for manufacturing a semiconductor device, comprising:

patterning a plurality of semiconductor fins on a semiconductor substrate;

replacing at least two of the plurality of semiconductor fins with a plurality of dummy fins comprising a dielectric material;

forming a gate structure on and around the plurality of semiconductor fins and the plurality of dummy fins;

forming a source/drain contact adjacent the gate structure;

forming a dummy gate on and around the plurality of semiconductor fins and the plurality of dummy fins;

removing the dummy gate and replacing the dummy gate with the gate structure, wherein the gate structure comprises at least one conductive material; and

removing a portion of the dummy gate between the plurality of dummy fins to create an opening between two dummy gate segments.

10. The method according to claim 9 , further comprising depositing a dielectric material in the opening between the two dummy gate segments.

11. The method according to claim 9 , wherein the removing and the replacing of the dummy gate with the gate structure comprises removing the two dummy gate segments and replacing of the two dummy gate segments with two gate structure segments.

12. The method according to claim 9 , wherein the plurality of semiconductor fins are formed in at least one active region, and the plurality of dummy fins are formed in at least one isolation region.

13. The method according to claim 9 , wherein the plurality of dummy fins are formed between two semiconductor fins of the plurality of semiconductor fins.

14. The method according to claim 9 , wherein the patterning of the plurality of semiconductor fins comprises:

forming a plurality of first hardmask portions on the semiconductor substrate, wherein the plurality of first hardmask portions comprise a first material;

replacing at least two of the plurality of first hardmask portions with a plurality of second hardmask portions, wherein the plurality of second hardmask portions comprise a second material different from the first material; and

transferring a pattern of the plurality of first and second hardmask portions to the semiconductor substrate to pattern the plurality of semiconductor fins.

15. The method according to claim 14 , wherein the replacing of the at least two of the plurality of semiconductor fins with the plurality of dummy fins comprises:

forming a dielectric fill layer on the semiconductor substrate and between the plurality of semiconductor fins;

selectively removing the plurality of second hardmask portions to expose underlying semiconductor fins of the plurality of semiconductor fins;

removing the exposed underlying semiconductor fins to create a plurality of openings in the dielectric fill layer; and

depositing a dielectric material in the plurality of openings in place of the removed semiconductor fins to form the plurality of dummy fins.

16. The method according to claim 14 , wherein the second material has an etch selectivity with respect to the first material.

17. A method for manufacturing a semiconductor device, comprising:

forming a plurality of first hardmask portions on a semiconductor substrate, wherein the plurality of first hardmask portions comprise a first material;

forming a plurality of second hardmask portions on the semiconductor substrate, wherein the plurality of second hardmask portions comprise a second material different from the first material;

transferring a pattern of the plurality of first and second hardmask portions to the semiconductor substrate to form a plurality of patterned substrate portions;

forming a dielectric fill layer on the semiconductor substrate and between the plurality of patterned substrate portions;

selectively removing the plurality of second hardmask portions to expose underlying patterned substrate portions of the plurality of patterned substrate portions;

removing the exposed underlying patterned substrate portions to create a plurality of openings in the dielectric fill layer; and

depositing a dielectric material in the plurality of openings in place of the removed patterned substrate portions to form a plurality of dummy elements.

18. The method according to claim 17 , further comprising:

removing the plurality of first hardmask portions;

recessing the dielectric fill layer; and

forming a gate structure on the recessed dielectric fill layer and on and around the plurality of patterned substrate portions and the plurality of dummy elements.

19. The method according to claim 18 , wherein forming the gate structure comprises:

forming a dummy gate on and around the plurality of patterned substrate portions and the plurality of dummy elements; and

removing the dummy gate and replacing the dummy gate with the gate structure, wherein the gate structure comprises at least one conductive material.

20. The method according to claim 17 , wherein the second material has an etch selectivity with respect to the first material.