Boost power factor correction conversion
In an example, a system comprises a boost power factor correction (PFC) converter including a thermistor, an inductor, and a transistor coupled to a common node. The system also comprises a PFC controller coupled to the common node. The PFC controller includes a comparator coupled to a threshold voltage source and to a non-control terminal of the transistor; a first flip-flop coupled to the comparator and to a control terminal of the transistor; a zero current detector coupled to the inductor; a timer coupled to the comparator and to the zero current detector; a second flip-flop coupled to the timer and to the control terminal of the transistor; an AND gate coupled to the first and second flip-flops; a third flip-flop coupled to the second flip-flop and to the control terminal of the transistor; and a fourth flip-flop coupled to the AND gate and to the control terminal of the transistor.
1. A system, comprising:
a boost power factor correction (PFC) converter including a thermistor having a lead coupled to a common node, an inductor having a lead coupled to the common node, and a transistor having a drain, a source, and a control terminal, the drain being connected to the common node and the source being connected to a circuit ground; and
a PFC controller coupled to the drain and the control terminal and including:
a comparator having a first input coupled to a threshold voltage source, a second input coupled to the common node, and having a comparator output;
a first flip-flop having a first input coupled to the comparator output, a clock input directly connected to the control terminal of the transistor, and having a first flip-flop output;
a zero current detector having an input coupled to the drain and having a zero current detector output;
a timer having a first input coupled to the comparator output, a second input, separate from the first input, coupled to the zero current detector output, and having a timer output;
a second flip-flop having a first input coupled to the timer output, a clock input directly connected to the control terminal of the transistor, and having a second flip-flop output;
an AND gate having a first input coupled to the first flip-flop output, a second input coupled to the second flip-flop output, and having an AND gate output;
a third flip-flop having a first input coupled to the output of the first flip-flop, a clock input directly connected to the control terminal of the transistor, and having a reduced on time output; and
a fourth flip-flop having a first input coupled to the AND gate output, a clock input directly connected to the control terminal of the transistor, and having an OVP 2 fault output.
2. The system of claim 1 , in which the clock input of the first flip-flop is an inverting clock input.
3. The system of claim 1 , in which the first flip-flop includes a third, data input adapted to receive a low signal.
4. The system of claim 1 , in which the first input of the timer is an inverting enable input and the second input of the timer is a clear input.
5. The system of claim 1 , in which the output of the first flip-flop is a non-inverting output and the output of the second flip-flop is an inverting output.
6. The system of claim 1 , in which the first input of the third flip-flop is a data input.
7. The system of claim 1 , in which the first input of the fourth flip-flop is a data input.
8. A system, comprising:
a boost power factor correction (PFC) converter including a thermistor having a lead coupled to a common node, an inductor having a lead coupled to the common node, and a transistor having drain and source terminals and a control terminal, the drain terminal being connected to the common node;
a comparator having a first input coupled to the common node, a second input adapted to receive a threshold voltage, and an output;
a first flip-flop having a set input coupled to the output of the comparator, a data input adapted to receive a low signal, an inverting clock input directly connected to the control terminal of the transistor, and an output;
a timer having an inverting enable input coupled to the output of the comparator, a clear input coupled to an output of a zero current detector, and an output;
a second flip-flop having a set input coupled to the output of the timer, a data input adapted to receive a low signal, an inverting clock input directly connected to the control terminal of the transistor, and an inverting output;
an AND gate having a first input coupled to the output of the first flip-flop, a second input coupled to the inverting output of the second flip-flop, and an output;
a third flip-flop having a data input coupled to the output of the first flip-flop, a clock input directly connected to the control terminal, and an output; and
a fourth flip-flop having a data input coupled to the output of the AND gate, a clock input directly connected to the control terminal, and an output.
9. A power factor correction controller comprising:
a comparator having a first input coupled to a threshold voltage source, a second input adapted to be coupled to a drain of a transistor, and having a comparator output;
a first flip-flop having a first input coupled to the comparator output, a clock input adapted to be directly connected to a control terminal of the transistor, and having a first flip-flop output;
a zero current detector having an input coupled to the drain and having a zero current detector output;
a timer having a first input coupled to the comparator output, a second input, separate from the first input, coupled to the zero current detector output, and having a timer output;
a second flip-flop having a first input coupled to the timer output, a clock input directly connected to the control terminal of the transistor, and having a second flip-flop output;
an AND gate having a first input coupled to the first flip-flop output, a second input coupled to the second flip-flop output, and having an AND gate output;
a third flip-flop having a first input coupled to the output of the first flip-flop, a clock input directly connected to the control terminal of the transistor, and having a reduced on time output; and
a fourth flip-flop having a first input coupled to the AND gate output, a clock input directly connected to the control terminal of the transistor, and having an OVP2 fault output.
10. The power factor correction controller of claim 9 in which the first flip-flop first input is a set input and the first flip-flop output is a Q output.
11. The power factor correction controller of claim 9 including a blanking circuit having an input coupled to the comparator output and having an output coupled to the first flip-flop first input.
12. The power factor correction controller of claim 9 in which the second flip-flop first input is a set input and the second flip-flop output is an inverted Q output.
13. The power factor correction controller of claim 9 in which the third flip-flop first input is a D input and the reduced time on output is a Q output.
14. The power factor correction controller of claim 9 in which the fourth flip-flop first input is a D input and the OVP2 fault output is a Q output.
15. The power factor correction controller of claim 9 including a driver circuit having a input coupled to the reduced on time output, an input coupled to the OVP2 fault output, and having an output adapted to be coupled to the gate of the transistor.