IP Library Granted Patent US 11,018,141
Granted Patent B2
US 11,018,141 · App. 16/011,652 · Granted May 25, 2021

Contacts and method of manufacturing the same

Inventors: Feng-Yi Chang (Tainan, TW); Fu-Che Lee (Taichung, TW)
Assignees: UNITED MICROELECTRONICS CORP.; Fujian Jinhua Integrated Circuit Co., Ltd.
H01L27/10888H01L27/10855H01L27/10885H01L27/10891
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Quick Facts
Patent No.
US 11,018,141
App. No.
16/011,652
Filed
Jun 19, 2018
Granted
May 25, 2021
Kind
B2
Art Unit
2817
USPC
257/296
Abstract

A method of manufacturing contacts is provided in the present invention, which include the steps of forming a plurality of mask bars on a substrate, forming a circular mask surrounding each mask bar, wherein the circular masks connect each other and define a plurality of opening patterns collectively with the mask bars, using the mask bars and the circular masks as etch masks to perform an etch process and to transfer the opening patterns and form a plurality recesses in the substrate, and filling up the recesses with metal to form contacts.

Claims (10)

1. A contact, comprising:

a substrate with a plurality of active areas isolated by isolating structures;

an interlayer dielectric directly on said isolating structures;

a plurality of bit line contacts in said interlayer dielectric and connecting with said active areas;

a plurality of storage node contacts in said interlayer dielectric and connecting with said active areas and said isolating structures, wherein one of said storage node contacts is provided at two sides of each of said bit line contacts and is isolated from said one of bit line contacts by said interlayer dielectric, and the bottom of said one of storage node contacts is level with the bottom of said each of bit line contacts;

a plurality of bit lines on said plurality of bit line contacts and connecting with said plurality of bit line contacts, wherein said plurality of storage node contacts are between said plurality of bit lines; and

spacer layers on sidewalls of said one of bit lines and on said interlayer dielectric.

2. The contact of claim 1 , wherein said each of bit line contacts is on the center of said one of active areas, and every two of said storage node contacts are on two opposite ends of said one of active areas respectively.

3. The contact of claim 1 , further comprising a plurality of word lines formed within said substrate and perpendicular to said plurality of bit lines, wherein said plurality of bit line contacts and said plurality of storage node contacts are between said plurality of word lines.

4. The contact of claim 1 , further comprising a contact plug on said each of storage node contacts.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 19, 2018
From: CHANG, FENG-YI; LEE, FU-CHE
To: UNITED MICROELECTRONICS CORP.; FUJIAN JINHUA INTEGRATED CIRCUIT CO., LTD.
Reel/Frame 046123/0882 →
Priority Claims (1)
CN 201710669727.2 · Aug 8, 2017 · national
Continuity (1)
Related Publication 20190051654A1 · Feb 14, 2019