Transistor and manufacturing method

1. A transistor comprising:

a gate electrode formed on a semiconductor substrate;

a source region formed on a surface of the semiconductor substrate and extended from the gate electrode; and

a drain region that is positioned to oppose the source region and formed on the surface of the semiconductor substrate without being brought into contact with the gate electrode, wherein the source region and the drain region are asymmetrical, wherein the drain region is formed in an L-shaped configuration denoting a two-directional arrangement, wherein the drain region is divided into an upper portion and a lower portion, wherein a top surface of the upper portion is coplanar with the surface of the semiconductor substrate and the lower portion is at a distance from the surface of the semiconductor substrate overlapped by the gate electrode, wherein in a cross-sectional view the lower portion extends towards the source region, and wherein a channel is formed between the source region and the drain region in such a manner that the channel deepens as it goes from the source region to the drain region.

2. The transistor according to claim 1 , wherein the source region, the gate electrode, and the drain region are linearly arranged.

3. The transistor according to claim 1 , wherein the source region, the gate electrode, and a portion of the drain region that is formed at a position deeper than the source region are linearly arranged.

4. The transistor according to claim 3 , wherein the portion of the drain region formed at the position deeper than the source region has a width of 5 to 20 nm.

5. The transistor according to claim 3 , wherein the portion of the drain region formed at a position deeper than the source region has a concentration of 1e19 cm −3 or higher.

6. The transistor according to claim 1 , wherein at a gate end of the gate electrode, the drain region is formed at a distance from the surface of the semiconductor substrate.

7. The transistor according to claim 1 , wherein the drain region is formed on a recessed portion.

8. The transistor according to claim 1 , wherein a distance between the drain region and a gate end of the gate electrode is set so as to form the channel at a position away from the surface of the semiconductor substrate and continuously without being interrupted by an electric field of a drain.

9. The transistor according to claim 1 , wherein an amount of protrusion of the drain region from a gate end of the gate electrode is set in consideration of preventing short-circuiting to the source region, gate length, avoiding channel shortening, and implantation alignment.

10. The transistor according to claim 1 , wherein a width of a high-resistance region of the drain region is set to form the channel at a position away from the surface of the semiconductor substrate and continuously without being interrupted by an electric field of a drain.

11. The transistor according to claim 1 , wherein a distance between the drain region and a gate end of the gate electrode is between 0 and 0.3 μm.

12. The transistor according to claim 1 , wherein an amount of protrusion of the drain region from a gate end of the gate electrode is within ±0.1 μm.

13. The transistor according to claim 10 , wherein the width of the high-resistance region of the drain region is between 0 and 0.3 μm.

14. A manufacturing method for manufacturing a transistor including:

forming a gate electrode on a semiconductor substrate;

forming a source region on a surface of the semiconductor substrate, wherein the source region extends from the gate electrode; and

forming and positioning a drain region to oppose the source region on the surface of the semiconductor substrate without being brought into contact with the gate electrode, wherein the source region and the drain region are asymmetrical, wherein the drain region is formed in an L-shaped configuration denoting a two-directional arrangement, wherein the drain region is divided into an upper portion and a lower portion, wherein a top surface of the upper portion is coplanar with the surface of the semiconductor substrate and the lower portion is at a distance from the surface of the semiconductor substrate overlapped by the gate electrode, wherein in a cross-sectional view the lower portion extends towards the source region, and wherein a channel is formed between the source region and the drain region in such a manner that the channel deepens as it goes from the source region to the drain region.

15. The manufacturing method according to claim 14 , comprising:

forming the drain region by performing resist patterning and ion implantation twice.

16. The manufacturing method according to claim 14 , comprising:

forming the drain region by performing resist patterning and ion implantation for canceling conductivity of a portion of the drain region coming into contact with the gate electrode.

17. The manufacturing method according to claim 14 , comprising:

forming the drain region by performing resist patterning and ion implantation after formation of a recessed portion.

18. The manufacturing method according to claim 14 , comprising:

forming the drain region by forming a recessed portion after performing resist patterning and ion implantation.