Multi-level memristor elements

1. A two-terminal multi-level memristor element synthesized from binary memristors, the multi-level memristor element comprising:

a plurality of binary memristor portions connected between first and second terminals of the multi-level memristor element, the binary memristor portions individually programmable between HI and LO resistance states;

wherein the binary memristor portions can be programmed to provide a variable multi-level resistance between the first and second terminals;

wherein the plurality of binary memristor portions are arranged in series between the first and second terminals; and

wherein the multi-level memristor element further comprises at least one offset resistor r 0 arranged in series with the plurality of binary memristor portions.

2. The multi-level memristor element of claim 1 , further comprising switching circuitry, the switching circuitry arranged to apply voltages or currents to individual binary memristor portions of the multi-level memristor element to program the respective binary memristor portions between HI and LO resistance states, and a program control module coupled with the switching circuitry, the program control module arranged to receive input data or weighting to be applied using the memristor element, and wherein the program control module controls the switching circuitry to program the binary memristor portions of the memristor element based on the received input data.

3. The multi-level memristor element of claim 2 , wherein the program control module is arranged to control the programming of the binary memristor portions of the memristor element based on the received input data to provide for a linear variation of conductance of the memristor element based relative to the received input data.

4. The multi-level memristor element of claim 1 , wherein the resistance of the at least one offset resistor r 0 is selected such that r 0 is greater than the combined total resistance of the binary memristor portions of the memristor element, when the binary memristor portions are set to the HI resistance state.

5. A two-terminal multi-level memristor element synthesised from binary memristors, the multi-level memristor element comprising:

a plurality of binary memristor portions connected between first and second terminals of the multi-level memristor element, the binary memristor portions individually programmable between HI and LO resistance states;

wherein the binary memristor portions can be programmed to provide a variable multi-level resistance between the first and second terminals;

wherein the binary memristor portions each comprise a binary memristor, to implement unary coding and wherein the multi-level memristor element is configured to perform dynamic element matching of the binary memristor portions; and

wherein the multi-level memristor portion comprises a dynamic element matching (DEM) module coupled with switching circuitry of the multi-level memristor portion, the DEM module arranged to receive a unary code word to define the resistance level of the multi-level memristor element, and wherein the DEM module controls the programming of the binary memristor portions of the multi-level memristor element to vary the bit assignments of the unary code word among the binary memristors of the multi-level memristor element.

6. A two-terminal multi-level memristor element synthesized from binary memristors, the multi-level memristor element comprising:

a plurality of binary memristor portions connected between first and second terminals of the multi-level memristor element, the binary memristor portions individually programmable between HI and LO resistance states;

wherein the binary memristor portions can be programmed to provide a variable multi-level resistance between the first and second terminals;

wherein the plurality of binary memristor portions are arranged in series between the first and second terminals; and

wherein the memristor element is configured to implement binary coding, wherein the binary memristor portions are configured such that the difference in impedance between the HI and LO resistance states (delta R) of a first binary memristor portion is scaled relative to the (delta R) of the other binary memristor portions of the multi-level memristor element.

7. The multi-level memristor element of claim 6 , wherein at least one of the series-connected binary memristor portions comprises a binary memristor and a parallel shunt resistor, wherein the resistance of the parallel shunt resistor is selected to provide for a (delta R) of the binary memristor portion which is scaled relative to the other binary memristor portions of the multi-level memristor element.

8. The multi-level memristor element of claim 6 , wherein at least some of the series-connected binary memristor portions each comprise first and second resistance components, wherein the first resistance component is connected in series with the other binary memristor portions and the second resistance component is connected in parallel with the first resistance component, wherein one of the first and second resistance components is a binary memristor and the other of the first and second resistance components is a shunt resistor; and

wherein for at least one of the binary memristor portions the second resistance component is connected in parallel with the series connection of first resistance components from a plurality of binary memristor portions.

9. The multi-level memristor element of claim 6 , wherein at least one of the series-connected binary memristor portions comprises a bank of binary memristors connected in parallel, the bank of binary memristors of a particular memristor portion being simultaneously switchable between HI and LO resistance states, wherein the number of parallel-connected binary memristors within the binary memristor portion is selected to provide for a (delta R) of the binary memristor portion which is scaled relative to the other binary memristor portions of the multi-level memristor element.

10. The multi-level memristor element of claim 6 , wherein the multi-level memristor element is arranged such that a first subset of the binary memristor portions each comprise a bank of binary memristors connected in parallel, and a second subset of the binary memristor portions each comprise a binary memristor and a parallel shunt resistor, the bank of binary memristors of a particular memristor portion being simultaneously switchable between HI and LO resistance states.

11. A synapse circuit for a neural network system comprising a two-terminal multi-level memristor element synthesized from binary memristors, the multi-level memristor element comprising:

a plurality of binary memristor portions connected between first and second terminals of the multi-level memristor element, the binary memristor portions individually programmable between HI and LO resistance states;

wherein the binary memristor portions can be programmed to provide a variable multi-level resistance between the first and second terminals; and

wherein the synapse circuit comprises:

an input to receive at least one data input signal indicative of a data input, the data input signal provided as a voltage or current;

an output to provide at least one data output current indicative of the data input times a defined weighting value; and

at least first and second data paths between the input and the output, the data paths comprising a two-terminal multi-level memristor element,

wherein the at least one data input signal is applied to at least one of the data paths,

wherein the resistance level of at least one multi-level memristor element is adjusted based on the defined weighting value, and

wherein the data output current is based on the current through said at least first and second data paths.

12. The synapse circuit of claim 11 , further comprising:

a weighting input to receive at least one weighting value indicative of a weighting to be applied to the data input, wherein the resistance level of at least one multi-level memristor element is adjusted based on the received weighting value.

13. The synapse circuit of claim 11 , wherein the synapse circuit is arranged such that:

the first data path is configured as a weighting path, wherein the resistance level of the multi-level memristor element of the first data path is adjusted based on the at least one weighting value, to provide a weight-dependent data current flowing through the weighting path, and

the second data path is configured as a reference path, wherein the resistance level of the multi-level memristor element of the second data path is set at a defined level, to provide a weight-independent reference current flowing through the reference path,

wherein the data output current is based on the difference between the weight-dependent data current and the weight-independent reference current.

14. The synapse circuit of claim 11 , wherein the synapse circuit is arranged such that:

the first data path is configured as a positive weighting path, wherein the resistance level of the multi-level memristor element of the first data path is adjusted based on a positive component of the at least one weighting value, to provide a positively-weighted data current flowing through the positive weighting path, and

the second data path is configured as a negative weighting path, wherein the resistance level of the multi-level memristor element of the second data path is adjusted based on a negative component of the at least one weighting value, to provide a negatively-weighted data current flowing through the negative weighting path, and

wherein the data output current is based on the difference between the positively- and negatively-weighted data currents.

15. The synapse circuit of claim 11 , wherein the synapse circuit is arranged such that:

an input is arranged to receive a differential data input signal indicative of a data input, the data input signal being differentially coded as a non-inverse signal and an inverse signal;

the first data path is configured as a weighting path to apply a weighting to the non-inverse signal, wherein the resistance level of the multi-level memristor element of the first data path is adjusted based on the at least one weighting value, to provide a first weighted current, and

the second data path is configured as a weighting path to apply a weighting to the inverse signal, wherein the resistance level of the multi-level memristor element of the second data path is adjusted based the at least one weighting value, to provide a second weighted current, and

wherein the data output current is based on the difference between the first and second weighted currents.