Vertically stacked semiconductor devices having vertical channel transistors

1. A semiconductor device comprising:

a semiconductor substrate having a main surface;

a first memory device and a second memory device formed over the substrate and at least partly stacked in a vertical direction intersecting the main surface,

wherein each of the first and second memory devices has a plurality of vertical transistors, wherein each of the vertical transistors is a gate-all-around junctionless nanowire field-effect transistor having no PN junction formed therein and having a vertical channel extending in the vertical direction that is fully surrounded by a gate electrode, and

wherein each of the first and second memory devices has a top electrode and a bottom electrode that are separated in the vertical direction; and

an interconnect layer configured to serve simultaneously as the top electrode of the first memory device and the bottom electrode of the second memory device.

2. The semiconductor device according to claim 1 , wherein the first memory device and the second semiconductor device overlap each other in a horizontal direction with respect to the main surface.

3. The semiconductor device according to claim 1 , wherein a vertical transistor of the first memory device and a vertical transistor of the second memory device share a common vertical channel.

4. The semiconductor device according to claim 1 , comprising two distinct and vertically separated gate levels, wherein a first gate level is arranged in the first memory device and the second gate level is arranged in the second memory device.

5. The semiconductor device according to claim 4 , wherein the first gate level and the second gate level are vertically separated by an interconnect level.

6. The semiconductor device according to claim 1 , wherein the first memory device and the second memory device physically share supply voltage lines (V DD , V SS ).

7. The semiconductor device according to claim 1 , wherein the first memory device and the second memory device physically share one or both of a common bitline (BL) and a complementary bitline (BLB).

8. The semiconductor device according to claim 7 , wherein the bitline and the complementary bitline are arranged in an interconnect level between the first memory device and the second memory device.

9. The semiconductor device according to claim 1 , wherein the first memory device and the second memory device are adapted to be controlled by two separate word lines (WL) arranged in an interconnect level between the first memory device and the second memory device.

10. The semiconductor device according to claim 1 , wherein each of the first memory device and the second memory device is a static random-access memory (SRAM) cell.

11. The semiconductor device according to claim 10 , wherein the SRAM cell is a six-transistor (6T) SRAM cell.

12. A method of manufacturing a semiconductor device, the method comprising:

providing a semiconductor substrate having a main surface;

forming a first memory device comprising a plurality of vertical transistors over the substrate; and

forming a second memory device comprising a plurality of vertical transistors over the substrate,

wherein the first memory device and the second memory device are at least partly stacked above each other in a vertical direction crossing the main surface,

wherein each of the first and second memory devices has a plurality of vertical transistors, wherein each of the vertical transistors is a gate-all-around junctionless nanowire field-effect transistor having no PN junction formed therein and having a vertical channel extending in the vertical direction that is fully surrounded by a gate electrode, and

wherein each of the first and second memory devices has a top electrode and a bottom electrode that are separated in the vertical direction; and

forming an interconnect layer configured to serve simultaneously as the top electrode of the first memory device and the bottom electrode of the second memory device.

13. The method according to claim 12 , wherein a vertical transistor of the first memory device and a vertical transistor of the second memory device are aligned with each other such that they share a common vertical channel.

14. The method according to claim 12 , further comprising forming the interconnect layer between the first memory device and the second memory device.

15. The method according to claim 12 , wherein a same mask is used for forming at least one layer of the first memory device and at least one layer of the second memory device.

16. The method according to claim 12 , further comprising:

forming vertical channels having opposite dopant types, comprising:

growing an n-type region,

growing a p-type region, and

etching the n-type region and the p-type region so as to form an n-type channel and a p-type channel, respectively.

17. The method according to claim 16 , wherein forming the vertical channels comprises epitaxially growing the n-type region and the p-type region.

18. The method according to claim 12 , wherein forming the vertical transistors of each of the first memory device and the second memory device comprises forming vertical channels, forming the vertical channels comprising:

etching the semiconductor substrate to form a first vertical channel,

etching the semiconductor substrate to form a second vertical channel,

doping the first vertical channel to form an n-type channel, and

doping the second vertical channel to form a p-type channel.

19. The method according to claim 18 , wherein doping the first vertical channel comprises forming a first oxide comprising an n-type dopant and diffusing the n-type dopant into the first vertical channel, and doping the second vertical channel comprises forming a second oxide comprising a p-type dopant and diffusion the p-type dopant into the second vertical channel.