Semiconductor device and manufacturing method thereof
View Patent ↗A semiconductor device includes a channel, source/drain structures, and a gate stack. The source/drain structures are on opposite sides of the channel. The gate stack is over the channel, and the gate stack includes a gate dielectric layer, a doped ferroelectric layer, and a gate electrode. The gate dielectric layer is over the channel. The doped ferroelectric layer is over the gate dielectric layer. The gate electrode is over the doped ferroelectric layer. A dopant concentration of the doped ferroelectric layer varies in a direction from the gate electrode toward the channel.
1. A semiconductor device comprising:
a channel;
source/drain structures on opposite sides of the channel; and
a gate stack over the channel, wherein the gate stack comprises:
a gate dielectric layer over the channel;
a doped ferroelectric layer over the gate dielectric layer, wherein the doped ferroelectric layer comprises a doped region and an undoped region, and a thickness of the undoped region of the doped ferroelectric layer is greater than a thickness of the doped region of the doped ferroelectric layer; and
a gate electrode over the doped ferroelectric layer.
2. The semiconductor device of claim 1 , wherein a dopant concentration of the doped ferroelectric layer decreases in the direction from the gate electrode toward the channel.
3. The semiconductor device of claim 1 , wherein a dopant concentration of the doped ferroelectric layer increases in the direction from the gate electrode toward the channel.
4. The semiconductor device of claim 1 , further comprising a barrier layer between the gate dielectric layer and the doped ferroelectric layer.
5. The semiconductor device of claim 1 , wherein the doped region of the doped ferroelectric layer is in contact with the gate electrode.
6. The semiconductor device of claim 5 , wherein dopants of the doped region are N-type, and the channel is P-type.
7. The semiconductor device of claim 5 , wherein dopants of the doped region are P-type, and the channel is N-type.
8. The semiconductor device of claim 1 , wherein the doped region of the doped ferroelectric layer is spaced apart from the gate electrode.
9. The semiconductor device of claim 8 , wherein dopants of the doped region are P-type, and the channel is P-type.
10. The semiconductor device of claim 8 , wherein dopants of the doped region are N-type, and the channel is N-type.
11. A method for manufacturing a semiconductor device comprising:
forming a dummy gate stack over a semiconductor fin in a substrate;
forming source/drain structures on the semiconductor fin;
forming a dielectric layer covering the source/drain structures and adjacent the dummy gate stack;
removing a gate electrode of the dummy gate stack to form a gate opening in the dielectric layer;
forming a doped ferroelectric layer in the gate opening, such that the doped ferroelectric layer has a first portion on a side surface of the semiconductor fin and a second portion on a top surface of the semiconductor fin, and a dopant concentration of the first portion of the doped ferroelectric layer is higher than a dopant concentration of the second portion of the doped ferroelectric layer; and
forming a gate electrode over the doped ferroelectric layer and in the gate opening.
12. The method of claim 11 , wherein forming the doped ferroelectric layer comprises:
forming a ferroelectric material layer in the gate opening; and
doping a top portion of the ferroelectric material layer to form the doped ferroelectric layer.
13. The method of claim 12 , wherein dopants of the doped ferroelectric layer and the semiconductor fin have different conductivity types.
14. The method of claim 11 , wherein forming the doped ferroelectric layer comprises:
forming a first ferroelectric material layer in the gate opening;
doping the first ferroelectric material layer; and
forming a second ferroelectric material layer over the first ferroelectric material layer to form the doped ferroelectric layer.
15. The method of claim 14 , wherein dopants of the doped ferroelectric layer and the semiconductor fin have the same conductivity type.
16. The method of claim 11 , further comprising forming a barrier layer in the gate opening, and the doped ferroelectric layer is formed over the barrier layer.
17. A method for manufacturing a semiconductor device comprising:
forming a gate stack over a channel of a substrate, comprising:
forming a gate dielectric layer over the channel of the substrate;
forming a doped ferroelectric layer over the gate dielectric layer, wherein a doping concentration of the doped ferroelectric layer is in a range of about 1E12 cm −2 to about 5E13 cm −2 ; and
forming a gate electrode over the doped ferroelectric layer; and
forming source/drain structures on opposite sides of the gate stack.
18. The method of claim 17 , wherein forming the doped ferroelectric layer comprises:
forming a ferroelectric material layer over the gate dielectric layer; and
doping a top portion of the ferroelectric material layer to form the doped ferroelectric layer.
19. The method of claim 17 , wherein forming the doped ferroelectric layer comprises:
forming a first ferroelectric material layer over the gate dielectric layer;
doping the first ferroelectric material layer; and
forming a second ferroelectric material layer over the first ferroelectric material layer to form the doped ferroelectric layer.
20. The method of claim 17 , further comprising forming a barrier layer over the gate dielectric layer, and the doped ferroelectric layer is formed over the barrier layer.