Selective internal gate structure for ferroelectric semiconductor devices
The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.
1. A semiconductor device, comprising:
a substrate;
first and second spacers on the substrate; and
a gate stack between the first and second spacers, the gate stack comprising:
a gate dielectric layer comprising a first portion on the substrate and a second portion on the first and second spacers;
an internal gate on the first and second portions of the gate dielectric layer;
a ferroelectric dielectric layer on the internal gate and in physical contact with the second portion of the gate dielectric layer through a non-linear surface; and
a gate electrode on the ferroelectric dielectric layer.
2. The semiconductor device of claim 1 , wherein the semiconductor device comprises a negative-capacitance field effect transistor (NCFET) device.
3. The semiconductor device of claim 1 , wherein the semiconductor device comprises a ferroelectric field effect transistor (FeFET) device.
4. The semiconductor device of claim 1 , further comprising a fin on the substrate, wherein the gate stack is on the fin.
5. The semiconductor device of claim 1 , wherein the ferroelectric dielectric layer is between the internal gate and the gate electrode.
6. The semiconductor device of claim 1 , wherein the ferroelectric dielectric layer is between the second portion of the gate dielectric layer and the gate electrode.
7. The semiconductor device of claim 1 , wherein an average thickness of the second portion of the gate dielectric layer is between about 40% and about 50% of a thickness of the first portion of the gate dielectric layer.
8. The semiconductor device of claim 1 , wherein the internal gate comprises a first metal layer on the gate dielectric layer and a second metal layer on the first metal layer.
9. The semiconductor device of claim 8 , wherein the first metal layer comprises:
a first portion on the first portion of the gate dielectric layer; and
a second portion on the second portion of the gate dielectric layer.
10. The semiconductor device of claim 9 , wherein the second portion of the first metal layer comprises a non-linear sidewall in physical contact with the second metal layer.
11. A method for forming a semiconductor device, comprising:
forming first and second spacers;
depositing a gate dielectric layer between the first and second spacers and on sidewalls of the first and second spacers;
forming an internal gate on the gate dielectric layer, wherein forming the internal gate comprises:
forming a first metal layer on the gate dielectric layer; and
selectively depositing a second metal layer on the first metal layer, comprising:
performing a cleaning process on the first metal layer; and
growing the second metal layer using the first metal layer as seed layer;
depositing a ferroelectric dielectric layer on the internal gate and gate dielectric layer; and
forming a gate electrode on the ferroelectric dielectric layer.
12. The method of claim 11 , further comprising etching back the gate dielectric layer using an anisotropic dry etching process.
13. The method of claim 11 , wherein forming the first metal layer comprises:
blanket depositing a first metal material on the gate dielectric layer;
forming a blocking layer on portions of the first metal material;
removing portions of the first metal material not covered by the blocking layer; and
removing the blocking layer.
14. The method of claim 13 , wherein removing the portions of the first metal material comprises performing a wet chemical etching process on the portions of the first metal material not covered by the blocking layer.
15. The method of claim 13 , wherein removing portions of the first metal material comprises forming a non-linear sidewall surface of the first metal material.
16. A method for forming a semiconductor device, comprising:
forming a fin;
forming first and second spacers on the fin;
depositing a gate dielectric layer on the fin and on sidewalls of the first and second spacers;
forming an internal gate on the gate dielectric layer, wherein forming the internal gate comprises:
depositing a first metal layer on the gate dielectric layer;
forming a blocking layer on portions of the first metal layer;
removing portions of the first metal layer not covered by the blocking layer;
removing the blocking layer;
performing a cleaning process on the first metal layer; and
selectively depositing a second metal layer using the first metal layer as a seed layer;
etching back the gate dielectric layer;
depositing a ferroelectric dielectric layer on the internal gate and gate dielectric layer; and
forming a gate electrode on the ferroelectric dielectric layer.
17. The method of claim 16 , wherein depositing the ferroelectric dielectric layer comprises depositing ferroelectric dielectric material directly on the gate dielectric layer.
18. The method of claim 16 , wherein etching back the gate dielectric layer comprises performing an anisotropic dry etching process on the gate dielectric layer.
19. The method of claim 16 , wherein selectively depositing the second metal layer comprises depositing tungsten.
20. The method of claim 16 , wherein removing portions of the first metal layer not covered by the blocking layer comprises forming a non-linear sidewall surface of the first metal material.