Output buffer circuit

1. An output buffer circuit, comprising:

an output terminal;

a transistor comprising:

a first terminal coupled to the output terminal;

a second terminal directly connected to a ground rail; and

a third terminal coupled to an output signal source;

a resistor comprising:

a first terminal coupled to a fourth terminal of the transistor; and

a second terminal connected to the ground rail.

2. The output buffer circuit of claim 1 , wherein:

the transistor is a first transistor; and

the output buffer circuit comprises:

a second transistor comprising:

a first terminal coupled to the fourth terminal of the first transistor;

a second terminal coupled to the ground rail; and

a third terminal coupled to the ground rail.

3. The output buffer circuit of claim 2 , wherein the fourth terminal of the first transistor is a backgate terminal, and the second transistor is configured to clamp the backgate terminal to the ground rail.

4. The output buffer circuit of claim 1 , wherein:

the transistor is a first transistor;

the resistor is a first resistor; and

the output buffer circuit comprises:

a second resistor comprising a first terminal coupled to the third terminal of the first transistor; and

a second transistor comprising:

a first terminal coupled to a second terminal of the second resistor; and

a second terminal coupled to the ground rail.

5. The output buffer circuit of claim 4 , wherein the resistor is configured to limit current flow from the fourth terminal to the second transistor.

6. The output buffer circuit of claim 1 , wherein the fourth terminal of the transistor is a backgate terminal, and the resistor is configured to decouple the backgate terminal from the ground rail.

7. An output buffer circuit, comprising:

an output terminal;

a transistor comprising:

a first terminal coupled to the output terminal;

a second terminal coupled to a ground rail; and

a third terminal coupled to an output signal source;

a first resistor comprising:

a first terminal coupled to a fourth terminal of the transistor; and

a second terminal coupled to the ground rail;

a second resistor comprising a first terminal coupled to a power supply rail; and

a diode comprising:

an anode terminal coupled to the fourth terminal of the transistor; and

a cathode terminal coupled to a second terminal of the second resistor.

8. The output buffer circuit of claim 7 , wherein:

the transistor is a first transistor; and

the output buffer circuit further comprises:

a second transistor comprising:

a first terminal coupled to the power supply rail;

a second terminal coupled to the ground rail; and

a third terminal coupled to the cathode terminal of the diode.

9. An output buffer circuit, comprising:

an output terminal;

a transistor comprising:

a drain terminal coupled to the output terminal;

a source terminal coupled to a ground rail; and

a backgate terminal coupled to a ground via a resistor;

wherein the resistor is configured to decouple the backgate terminal from the ground rail at frequencies higher than a selected frequency.

10. The output buffer circuit of claim 9 , further comprising a clamp transistor coupled in parallel with the resistor, and configured to couple the backgate terminal to the ground rail.

11. The output buffer circuit of claim 9 , wherein the resistor has a resistance of approximately 1 kiloohm.

12. The output buffer circuit of claim 9 , wherein:

the transistor is a first transistor;

the resistor is a first resistor; and

the output buffer circuit comprises:

a second transistor comprising:

a drain terminal coupled to a gate terminal of the first transistor via a second resistor; and

a source terminal coupled to the ground rail.

13. The output buffer circuit of claim 12 , wherein the second resistor has a resistance of approximately 10 kiloohms.

14. The output buffer circuit of claim 9 , wherein:

the resistor is a first resistor; and

the output buffer circuit comprises:

a second resistor comprising a first terminal coupled to a power supply rail;

a diode comprising:

an anode terminal coupled to the backgate terminal of the transistor; and

a cathode terminal coupled to a second terminal of the second resistor.

15. The output buffer circuit of claim 14 , further comprising a clamp transistor coupled in parallel with the second resistor.

16. The output buffer circuit of claim 14 , wherein the second resistor has a resistance of approximately 10 kiloohms.

17. An integrated circuit, comprising:

an output buffer circuit including:

an output terminal;

a first transistor comprising:

a first terminal coupled to the output terminal;

a second terminal connected to a ground rail; and

a third terminal coupled to an output signal source;

a first resistor comprising:

a first terminal coupled to a fourth terminal of the first transistor; and

a second terminal connected to the ground rail;

a second resistor comprising a first terminal coupled to the third terminal of the first transistor;

a second transistor comprising:

a first terminal coupled to a second terminal of the second resistor; and

a second terminal coupled to the ground rail;

a third resistor comprising a first terminal coupled to a power supply rail; and

a diode comprising:

an anode terminal coupled to the fourth terminal of the first transistor; and

a cathode terminal coupled to a second terminal of the second resistor.

18. The integrated circuit of claim 17 , wherein the output buffer circuit further comprises:

a third transistor comprising:

a first terminal coupled to the power supply rail;

a second terminal coupled to the ground rail; and

a third terminal coupled to the cathode terminal of the diode.

19. The integrated circuit of claim 17 , wherein:

the first resistor has a resistance of approximately 1 kiloohm; and

the second resistor has a resistance of approximately 10 kiloohms.