Reducing resource requirements for high-frequency counter arrays
Systems and method include receiving counter update requests that are at a maximum frequency of f counters ; sending the counter update requests to a main block of counters that operate at a maximum frequency of f main , where (f main )≥(f counters )/2; and responsive to a block of the main block of counters experiencing an overflow, sending corresponding counter update requests for the block of the main block of counters experiencing the overflow to a cache counter block that operates at a maximum frequency of f cache , where (f main )≥(f cache ) and (f cache )≥(f counters )−(f main ). The counter update requests can be for Y×K total counters, and the main block of counters can include Y blocks of counters each block having K counters, Y and K are positive integers. (f main )≥(f counters )/2 ensures only one block of the main block of counters overflows simultaneously.
1. A method comprising:
receiving counter update requests that are at a maximum frequency of f counters ;
sending the counter update requests to a main block of counters that operate at a maximum frequency of f main , where (f main )≥(f counters )/2; and
responsive to a block of the main block of counters experiencing an overflow, sending corresponding counter update requests for the block of the main block of counters experiencing the overflow to a cache counter block that operates at a maximum frequency of f cache , where (f main )≥(f cache ) and (f cache )≥(f counters )−(f main ).
2. The method of claim 1 , wherein the counter update requests are for Y×K total counters, and wherein the main block of counters includes Y blocks of counters each block having K counters, Y and K are positive integers.
3. The method of claim 1 , wherein (f main )≥(f counters )/2 ensures only one block of the main block of counters overflows simultaneously.
4. The method of claim 1 , further comprising
subsequent to the block of the main block of counters experiencing the overflow and the sending the corresponding counter update requests to the cache counter block, determining a second block of the main block of counters is experiencing an overflow; and
sending data in the cache counter block to the main block and sending corresponding counter update requests for the second block to the cache counter block.
5. The method of claim 1 , further comprising
converting a clock associated with the counter update requests to a clock associated with the main block of counters.
6. The method of claim 1 , wherein the method is performed in one of an Application Specific Integrated Circuit and a Field Programmable Gate Array (FPGA).
7. The method of claim 1 , wherein the method is performed in a statistics circuit connected to switching circuitry and the counter update requests are associated with monitoring for the switching circuitry.
8. The method of claim 1 , wherein the counter update requests are associated with monitoring packet services.
9. A system comprising:
circuitry configured to
receive counter update requests that are at a maximum frequency of f counters ,
send the counter update requests to a main block of counters that operate at a maximum frequency of f main , where (f main )≥(f counters )/2, and
responsive to a block of the main block of counters experiencing an overflow, send corresponding counter update requests for the block of the main block of counters experiencing the overflow to a cache counter block that operates at a maximum frequency of f cache , where (f main )≥(f cache ) and (f cache )≥(f counters )−(f main ).
10. The system of claim 9 , wherein the counter update requests are for Y×K total counters, and wherein the main block of counters includes Y blocks of counters each block having K counters, Y and K are positive integers.
11. The system of claim 9 , wherein (f main )≥(f counters )/2 ensures only one block of the main block of counters overflows simultaneously.
12. The system of claim 9 , further comprising
circuitry configured to
subsequent to the block of the main block of counters experiencing the overflow, determine a second block of the main block of counters is experiencing an overflow, and
send data in the cache counter block to the main block and sending corresponding counter update requests for the second block to the cache counter block.
13. The system of claim 9 , further comprising
circuitry configured to
convert a clock associated with the counter update requests to a clock associated with the main block of counters.
14. The system of claim 9 , wherein the circuitry includes one of an Application Specific Integrated Circuit and a Field Programmable Gate Array (FPGA).
15. The system of claim 9 , wherein the counter update requests are associated with monitoring for switching circuitry.
16. The system of claim 9 , wherein the counter update requests are associated with monitoring packet services.
17. A statistics circuit comprising:
update request router and overflow detection circuitry configured to receive counter update requests that are at a maximum frequency of f counters ;
a main block of counters that operate at a maximum frequency of f main , where (f main )≥(f counters )/2, each block is connected to the update request router and overflow detection circuitry; and
a cache counter block that operates at a maximum frequency of f cache , where (f main )≥(f cache ) and (f cache )≥(f counters )−(f main ), wherein, responsive to a block of the main block of counters experiencing an overflow, corresponding counter update requests for the block experiencing the overflow are provided to the cache counter block.
18. The statistics circuit of claim 17 , wherein the counter update requests are for Y×K total counters, and wherein the main block of counters includes Y blocks of counters each block having K counters, Y and K are positive integers.
19. The statistics circuit of claim 17 , wherein (f main )≥(f counters )/2 ensures only one block of the main block of counters overflows simultaneously.
20. The statistics circuit of claim 17 , further comprising
clock domain crossing circuitry between update request router and overflow detection circuitry, the main block of counters, and the cache counter block, and configured to perform clock conversions.