Continuously changing system clock in a packet processing module based on load determined by deterministic feedback signals
A packet processing module includes circuitry configured to receive feedback signals from each of N first-in, first-out (FIFOs), N is an integer that is greater than or equal to 1, determine a clock speed for the packet processing module based on the received feedback signals, and program a phase lock loop (PLL) based on the determined clock speed where the PLL provides a module clock at the determined clock speed to a packet processing circuit which is configured to receive and process packets from the N FIFOs. The feedback signals are a deterministic representation of processing needed for the packet processing circuit given a current state of packets available.
1. A packet processing module comprising circuitry configured to:
receive feedback signals from each of N first-in, first-out (FIFOs), N is an integer that is greater than or equal to 1,
determine a clock speed for the packet processing module based on the received feedback signals, and
program a phase lock loop (PLL) based on the determined clock speed where the PLL provides a module clock at the determined clock speed to a packet processing circuit which is configured to receive and process packets from the N FIFOs,
wherein the feedback signals are each packet available signal which is asserted for each of the N FIFOs based on detection of a complete packet therein for processing by the packet processing circuit, and
wherein the determined clock speed is set based on a number of packet available signals asserted at a given time multiplied by a minimum clock frequency which is set equal to a maximum clock frequency divided by N.
2. The packet processing module of claim 1 , wherein the feedback signals are each a fill level of a given FIFO of the N FIFOs.
3. The packet processing module of claim 1 , wherein the feedback signals are a deterministic representation of processing needed for the packet processing circuit given a current state of packets available.
4. The packet processing module of claim 1 , wherein the circuitry is further configured to
continuously program the PLL based on the received feedback signals over time.
5. The packet processing module of claim 1 , wherein the packet processing circuit is configured to perform processing of control information in the received packets, processing of data content in the received packets, and a combination thereof.
6. The packet processing module of claim 1 , wherein the packet processing circuit is configured to perform processing of control information in the received packets.
7. The packet processing module of claim 1 , wherein the packet processing circuit is configured to perform processing of data content in the received packets.
8. A method comprising steps of:
receiving feedback signals from each of N first-in, first-out (FIFOs), N is an integer that is greater than or equal to 1;
determining a clock speed for a packet processing module based on the received feedback signals; and
programming a phase lock loop (PLL) based on the determined clock speed where the PLL provides a module clock at the determined clock speed to a packet processing circuit in the packet processing module which is configured to receive and process packets from the N FIFOs,
wherein the feedback signals are each a packet available signal which is asserted for each of the N FIFOs based on detection of a complete packet therein for processing by the packet processing circuit, and
wherein the determined clock speed is set based on a number of packet available signals asserted at a given time multiplied by a minimum clock frequency which is set equal to a maximum clock frequency divided by N.
9. The method of claim 8 , wherein the feedback signals are each a fill level of a given FIFO of the N FIFOs.
10. The method of claim 8 , wherein the feedback signals are a deterministic representation of processing needed for the packet processing circuit given a current state of packets available.
11. The method of claim 8 , wherein the steps further include
continuously programming the PLL based on the received feedback signals over time.
12. The method of claim 8 , wherein the packet processing circuit is configured to perform processing of control information in the received packets, processing of data content in the received packets, and a combination thereof.
13. A packet processing module comprising:
N first-in, first-out (FIFOs), N is an integer that is greater than or equal to 1;
a programming state machine implemented in circuitry and configured to receive feedback signals from each of the N FIFOs and to program a phase lock loop (PLL) based thereon; and
a packet processing circuit configured to receive packets from the N FIFOs, wherein the packet processing circuit receives a module clock from the PLL with a speed determined by the programming state machine,
wherein the feedback signals are each a packet available signal which is asserted for each of the N FIFOs based on detection of a complete packet therein for processing by the packet processing circuit, and
wherein the determined clock speed based on a number of packet available signals asserted at a given time multiplied by a minimum clock frequency which is set equal to a maximum clock frequency divided by N.
14. The packet processing module of claim 13 , wherein the feedback signals are each a fill level of a given FIFO of the N FIFOs.
15. The packet processing module of claim 13 , wherein the feedback signals are a deterministic representation of processing needed for the packet processing circuit given a current state of packets available.
16. The packet processing module of claim 13 , wherein the steps further include
continuously programming the PLL based on the received feedback signals over time.
17. The packet processing module of claim 13 , wherein the packet processing circuit is configured to perform processing of control information in the received packets, processing of data content in the received packets, and a combination thereof.