Hierarchical clock tree construction based on constraints
View Patent ↗A method of automatically constructing a hierarchical clock tree for an integrated circuit may include constructing a global clock tree on a first level based on first-level constraints, pushing the global clock tree to partitions on a second level, and generating second-level constraints for the partitions on the second level. The second-level constraints may be included in configuration files that may be generated for the partitions on the second level. The first-level constraints may be included in a first-level configuration file that is user-modifiable. The second-level constraints may include information for replicating multiple instantiated partitions on the second level. The method may further include modifying terminal names and/or configurations after pushdown. The method may further include creating infrastructure to analyze timing of the global clock tree.
1. A method of automatically constructing a hierarchical clock tree for an integrated circuit, the method comprising:
constructing a global clock tree on a first level based on first-level constraints;
pushing at least a portion of the global clock tree including one or more clock cells of the global clock tree into one or more partitions on a second level; and
generating second-level constraints for the one or more partitions on the second level.
2. The method of claim 1 , wherein the second-level constraints include information for replicating multiple instantiated partitions on the second level.
3. The method of claim 1 , further comprising modifying one or more terminal names after pushdown.
4. The method of claim 1 , further comprising modifying one or more terminal configurations after pushdown.
5. The method of claim 1 , further comprising generating configuration files including the second-level constraints for the one or more partitions on the second level.
6. The method of claim 1 , wherein the first-level constraints are included in a first-level configuration file that is user-modifiable.
7. The method of claim 1 , further comprising creating infrastructure to analyze timing of the global clock tree.
8. The method of claim 7 , wherein creating the infrastructure comprises replicating one or more cells and one or more routes for multiple instance partitions.
9. The method of claim 8 , wherein creating the infrastructure further comprises adding clock sinks near endpoints of the global clock tree.
10. The method of claim 9 , further comprising calculating timing for the endpoints of the global clock tree based on the first-level constraints.
11. The method of claim 10 wherein calculating timing for the endpoints comprises calculating latency.
12. The method of claim 10 wherein calculating timing for the endpoints comprises calculating skew.
13. The method of claim 1 , wherein:
the first level is a top level; and
the second level is a block level.
14. The method of claim 1 , wherein the method is performed in a user-interactive mode.
15. The method of claim 1 , wherein constructing the global clock tree on the first level based on first-level constraints comprises:
placing clock cells for the global clock tree on the first level based on the first-level constraints;
modifying a first-level netlist to include new nets for the clock cells; and
routing segments for the global clock tree based on the first-level constraints.
16. A method of automatically constructing a hierarchical clock tree for an integrated circuit, the method comprising:
placing cells for a global clock tree on a first level based on first-level constraints;
routing segments for the global clock tree on the first level based on the first-level constraints;
creating clock routes for one or more multiple instantiated partitions on a second level based on the global clock tree;
pushing at least a portion of the global clock tree including one or more clock cells of the global clock tree into one or more partitions on the second level; and
generating second-level constraints for the global clock tree in the one or more partitions on the second level, including the one or more multiple instantiated partitions.
17. The method of claim 16 , wherein creating clock routes for the one or more multiple instantiated partitions further comprises replicating route segments that cross from one or more non-master partitions to one or more master partitions.
18. The method of claim 17 , wherein creating clock routes for the one or more multiple instantiated partitions further comprises renaming route segments that cross from non-master to master partitions.
19. The method of claim 17 , wherein creating clock routes for the one or more multiple instantiated partitions further comprises trimming route segments to prevent the route segments from passing into one or more non-master MIM instances.
20. A method of constructing a hierarchical clock tree for an integrated circuit, the method comprising:
placing cells based on a global clock tree distribution topology with constraints;
generating routes based on the global clock tree distribution topology with constraints;
pushing at least a portion of the cells and routes of the global clock tree distribution topology from a first level into one or more partitions on a second level; and
implementing the global clock tree on the second level using engineering change orders (ECOs).