IP Library Granted Patent US 11,024,655
Granted Patent B2
US 11,024,655 · App. 16/724,666 · Granted Jun 1, 2021

Liquid crystal display device and method for manufacturing the same

Inventors: Shunpei Yamazaki (Tokyo, JP); Kaoru Hatano (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L27/124G02F1/1333G02F1/1343G02F1/136213H01L27/1225H01L27/1259H01L29/24H01L29/7869H01L29/78618H01L29/78696G02F1/136227G02F1/136231G02F2201/50
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Quick Facts
Patent No.
US 11,024,655
App. No.
16/724,666
Granted
Jun 1, 2021
Kind
B2
Abstract

Provided is a method to manufacture a liquid crystal display device in which a contact hole for the electrical connection of the pixel electrode and one of the source and drain electrode of a transistor and a contact hole for the processing of a semiconductor layer are formed simultaneously. The method contributes to the reduction of a photography step. The transistor includes an oxide semiconductor layer where a channel formation region is formed.

Claims (49)

1. A display device comprising:

a pixel portion comprising:

a transistor comprising:

a gate electrode over and in contact with an insulating surface;

a first insulating layer over the gate electrode; and

a metal oxide layer electrically connected to a channel formation region of the transistor;

a second insulating layer over the metal oxide layer; and

a first conductive layer over the second insulating layer, the first conductive layer being electrically connected to the metal oxide layer; and

a connecting portion comprising:

a second conductive layer over and in contact with the insulating surface;

the first insulating layer over the second conductive layer;

an oxide semiconductor layer over the first insulating layer;

the second insulating layer over the oxide semiconductor layer; and

a third conductive layer over the second insulating layer,

wherein the gate electrode and the channel formation region overlap each other,

wherein each of the first insulating layer, the oxide semiconductor layer, and the second insulating layer comprises a contact hole,

wherein the third conductive layer is electrically connected to the second conductive layer through the contact hole of each of the first insulating layer, the oxide semiconductor layer, and the second insulating layer, and

wherein the third conductive layer is in contact with a side surface of the second insulating layer.

2. A display device comprising:

a pixel portion comprising:

a transistor comprising:

a gate electrode over and in contact with an insulating surface;

a first insulating layer over the gate electrode; and

a metal oxide layer electrically connected to a channel formation region of the transistor;

a second insulating layer over the metal oxide layer; and

a first conductive layer over the second insulating layer, the first conductive layer being electrically connected to the metal oxide layer; and

a connecting portion comprising:

a second conductive layer over and in contact with the insulating surface;

the first insulating layer over the second conductive layer;

an oxide semiconductor layer over the first insulating layer;

the second insulating layer over the oxide semiconductor layer; and

a third conductive layer over the second insulating layer,

wherein the gate electrode and the channel formation region overlap each other,

wherein each of the first insulating layer, the oxide semiconductor layer, and the second insulating layer comprises a contact hole,

wherein the third conductive layer is electrically connected to the second conductive layer through the contact hole of each of the first insulating layer, the oxide semiconductor layer, and the second insulating layer,

wherein the third conductive layer is in contact with a side surface of the second insulating layer, and

wherein each of the gate electrode and the second conductive layer has a layered structure in which a copper layer is over a titanium layer.

3. The display device according to claim 1 ,

wherein the oxide semiconductor layer is in contact with an upper surface of the first insulating layer.

4. The display device according to claim 2 ,

wherein the oxide semiconductor layer is in contact with an upper surface of the first insulating layer.

5. The display device according to claim 1 , wherein the oxide semiconductor layer contains In, Ga, and Zn.

6. The display device according to claim 2 , wherein the oxide semiconductor layer contains In, Ga, and Zn.

7. The display device according to claim 1 , further comprising:

a liquid crystal material over the first conductive layer.

8. The display device according to claim 2 , further comprising:

a liquid crystal material over the first conductive layer.

9. The display device according to claim 1 , wherein the channel formation region includes crystals with c-axis alignment.

10. The display device according to claim 2 , wherein the channel formation region includes crystals with c-axis alignment.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 24, 2019
From: YAMAZAKI, SHUNPEI; HATANO, KAORU
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 051361/0360 →
Priority Claims (1)
JP 2010-204930 · Sep 13, 2010 · national
Continuity (5)
Continuation 15916362 · Mar 9, 2018
Continuation 15088200 · Apr 1, 2016
Continuation 14023515 · Sep 11, 2013
Continuation 13227092 · Sep 7, 2011
Related Publication 20200144299A1 · May 7, 2020