Transistor, array substrate and method of manufacturing the same, display device
The present disclosure provides a transistor, an array substrate and a method of manufacturing the array substrate, and a display device. The method of manufacturing the array substrate comprises: depositing a plurality of silicon oxide layers on an active layer of a transistor; and depositing a silicon oxynitride layer over the plurality of silicon oxide layers.
1. A method of manufacturing an array substrate, comprising:
depositing a plurality of silicon oxide layers on an active layer of a transistor, including:
depositing a first silicon oxide layer on the active layer; and
depositing a second silicon oxide layer above the first silicon oxide layer by using nitrogen monoxide and silane gases with a mass flow ratio of the nitrogen monoxide to silane gases being 75:1-85:1;
depositing a silicon oxynitride layer on the plurality of silicon oxide layers by using nitrogen monoxide and silane gases with a mass flow ratio of the nitrogen monoxide to silane gases being larger than 60:1; and
annealing the silicon oxynitride layer at an annealing temperature not higher than 250° C.,
wherein the silicon oxide layers and the silicon oxynitride layer constitute a passivation layer of the array substrate.
2. The method of manufacturing an array substrate according to claim 1 , wherein a hydrogen content in the first silicon oxide layer is higher than that in other silicon oxide layers.
3. The method of manufacturing an array substrate according to claim 2 , wherein a thickness of the first silicon oxide layer ranges from 200 Å to 800 Å.
4. The method of manufacturing an array substrate according to claim 2 , wherein a thickness of the second silicon oxide layer ranges from 500 Å to 1000 Å.
5. The method of manufacturing an array substrate according to claim 1 ,
wherein, when the first silicon oxide layer is deposited, a mass flow ratio of the nitrogen monoxide to silane gases is 35:1-45:1.
6. The method of manufacturing an array substrate according to claim 5 , wherein the step of depositing a plurality of silicon oxide layers on an active layer further includes:
depositing a third silicon oxide layer using nitrogen monoxide and silane gases, between the steps of depositing the first silicon oxide layer and the second silicon oxide layer,
wherein, when the third silicon oxide layer is deposited, a mass flow ratio of the nitrogen monoxide to silane gases is 45:1-75:1.
7. The method of manufacturing an array substrate according to claim 5 , wherein the silane gases are monosilane.
8. The method of manufacturing an array substrate according to claim 1 , wherein a temperature for depositing the silicon oxynitride layer is 200° C.-350° C.
9. The method of manufacturing an array substrate according to claim 1 , wherein an oxygen content in the first silicon oxide layer is lower than that in other silicon oxide layers.
10. A transistor, including:
an active layer;
a plurality of silicon oxide layers on the active layer; and
a silicon oxynitride layer on the plurality of silicon oxide layers,
wherein the silicon oxide layers and the silicon oxynitride layer constitute a passivation layer of the array substrate,
the plurality of silicon oxide layers comprises:
a first silicon oxide layer on the active layer; and
a second silicon oxide layer above the first silicon oxide layer,
wherein the second silicon oxide layer is deposited by using nitrogen monoxide and silane gases with a mass flow ratio of the nitrogen monoxide to silane gases being 75:1-85:1,
the silicon oxynitride layer is deposited by using nitrogen monoxide and silane bases with a mass flow ratio of the nitrogen monoxide to silane gases being larger than 60:1, and
the silicon oxynitride layer is annealed at an annealing temperature not higher than 250′C.
11. The transistor according to claim 10 , wherein a hydrogen content in the first silicon oxide layer is higher than that in other silicon oxide layers.
12. The transistor according to claim 10 , wherein an oxygen content in the first silicon oxide layer is lower than that in other silicon oxide layers.
13. The transistor according to claim 10 , wherein a thickness of the first silicon oxide layer ranges from 200 Å to 800 Å.
14. The transistor according to claim 13 , wherein a thickness of the second silicon oxide layer ranges from 500 Å to 1000 Å.
15. An array substrate, including a transistor array, wherein at least a portion of transistors in the transistor array include:
an active layer;
a plurality of silicon oxide layers on the active layer; and
a silicon oxynitride layer on the plurality of silicon oxide layers,
wherein the silicon oxide layers and the silicon oxynitride layer constitute a passivation layer of the array substrate,
the plurality of silicon oxide layers comprises:
a first silicon oxide layer on the active layer; and
a second silicon oxide layer above the first silicon oxide layer,
wherein the second silicon oxide layer is deposited by using nitrogen monoxide and silane gases with a mass flow ratio of the nitrogen monoxide to silane gases being 75:1-85:1,
the silicon oxynitride layer is deposited by using nitrogen monoxide and silane gases with a mass flow ratio of the nitrogen monoxide to silane gases being larger than 60:1, and
the silicon oxynitride layer is annealed at an annealing temperature not higher than 250° C.
16. The array substrate according to claim 15 , wherein a hydrogen content in the first silicon oxide layer is higher than that in other silicon oxide layers.
17. The array substrate according to claim 15 , wherein an oxygen content in the first silicon oxide layer is lower than that in other silicon oxide layers.
18. The array substrate according to claim 15 , wherein a thickness of the first silicon oxide layer ranges from 200 Å to 800 Å.
19. A display device, comprising the array substrate according to claim 15 .